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Initial implementation of MipsTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3482,6 +3482,26 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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}
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bool
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MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
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// No global is ever allowed as a base.
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if (AM.BaseGV)
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return false;
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switch (AM.Scale) {
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case 0: // "r+i" or just "i", depending on HasBaseReg.
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break;
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case 1:
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if (!AM.HasBaseReg) // allow "r+i".
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break;
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return false; // disallow "r+r" or "r+r+i".
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default:
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return false;
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}
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return true;
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}
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bool
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bool
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MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// The Mips target isn't yet aware of offsets.
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// The Mips target isn't yet aware of offsets.
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@ -357,6 +357,8 @@ namespace llvm {
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std::vector<SDValue> &Ops,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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SelectionDAG &DAG) const;
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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41
test/CodeGen/Mips/addressing-mode.ll
Normal file
41
test/CodeGen/Mips/addressing-mode.ll
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@ -0,0 +1,41 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s
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@g0 = common global i32 0, align 4
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@g1 = common global i32 0, align 4
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; Check that LSR doesn't choose a solution with a formula "reg + 4*reg".
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;
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; CHECK: $BB0_2:
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; CHECK-NOT: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
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define i32 @f0(i32 %n, i32 %m, [256 x i32]* nocapture %a, [256 x i32]* nocapture %b) nounwind readonly {
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entry:
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br label %for.cond1.preheader
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for.cond1.preheader:
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%s.022 = phi i32 [ 0, %entry ], [ %add7, %for.inc9 ]
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%i.021 = phi i32 [ 0, %entry ], [ %add10, %for.inc9 ]
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br label %for.body3
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for.body3:
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%s.120 = phi i32 [ %s.022, %for.cond1.preheader ], [ %add7, %for.body3 ]
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%j.019 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ]
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%arrayidx4 = getelementptr inbounds [256 x i32]* %a, i32 %i.021, i32 %j.019
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%0 = load i32* %arrayidx4, align 4
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%arrayidx6 = getelementptr inbounds [256 x i32]* %b, i32 %i.021, i32 %j.019
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%1 = load i32* %arrayidx6, align 4
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%add = add i32 %0, %s.120
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%add7 = add i32 %add, %1
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%add8 = add nsw i32 %j.019, %m
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%cmp2 = icmp slt i32 %add8, 64
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br i1 %cmp2, label %for.body3, label %for.inc9
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for.inc9:
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%add10 = add nsw i32 %i.021, %n
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%cmp = icmp slt i32 %add10, 64
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br i1 %cmp, label %for.cond1.preheader, label %for.end11
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for.end11:
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ret i32 %add7
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}
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