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Add initial support for selecting constant materializations that require constant
pool loads on X86 in fast isel. This isn't actually used yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22,6 +22,7 @@ namespace llvm {
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class ConstantFP;
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class ConstantFP;
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class MachineBasicBlock;
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class MachineBasicBlock;
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class MachineConstantPool;
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class MachineFunction;
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class MachineFunction;
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class MachineRegisterInfo;
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class MachineRegisterInfo;
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class TargetData;
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class TargetData;
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@ -215,9 +216,14 @@ protected:
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/// from a specified index of a superregister.
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/// from a specified index of a superregister.
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unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
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unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
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void UpdateValueMap(Instruction* I, unsigned Reg);
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void UpdateValueMap(Value* I, unsigned Reg);
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unsigned createResultReg(const TargetRegisterClass *RC);
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unsigned createResultReg(const TargetRegisterClass *RC);
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virtual unsigned TargetSelectConstantPoolLoad(Constant* C,
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MachineConstantPool* MCP) {
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return 0;
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}
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private:
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private:
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bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode);
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bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode);
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@ -80,7 +80,7 @@ unsigned FastISel::getRegForValue(Value *V) {
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/// NOTE: This is only necessary because we might select a block that uses
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/// NOTE: This is only necessary because we might select a block that uses
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/// a value before we select the block that defines the value. It might be
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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/// possible to fix this by selecting blocks in reverse postorder.
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void FastISel::UpdateValueMap(Instruction* I, unsigned Reg) {
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void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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if (!ValueMap.count(I))
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if (!ValueMap.count(I))
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ValueMap[I] = Reg;
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ValueMap[I] = Reg;
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else
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else
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@ -22,6 +22,7 @@
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#include "llvm/InstrTypes.h"
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#include "llvm/InstrTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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using namespace llvm;
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@ -51,6 +52,8 @@ private:
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bool X86SelectStore(Instruction *I);
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bool X86SelectStore(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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unsigned TargetSelectConstantPoolLoad(Constant *C, MachineConstantPool* MCP);
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};
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};
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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@ -401,6 +404,91 @@ X86FastISel::TargetSelectInstruction(Instruction *I) {
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return false;
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return false;
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}
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}
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unsigned X86FastISel::TargetSelectConstantPoolLoad(Constant *C,
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MachineConstantPool* MCP) {
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unsigned CPLoad = getRegForValue(C);
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if (CPLoad != 0)
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return CPLoad;
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// Can't handle PIC-mode yet.
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if (TM.getRelocationModel() == Reloc::PIC_)
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return 0;
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MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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return false;
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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unsigned ResultReg = createResultReg(RC);
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if (isa<GlobalValue>(C)) {
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if (X86SelectConstAddr(C, ResultReg))
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return ResultReg;
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else
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return 0;
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}
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unsigned MCPOffset = MCP->getConstantPoolIndex(C, 0);
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addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
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UpdateValueMap(C, ResultReg);
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return ResultReg;
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}
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namespace llvm {
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namespace llvm {
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llvm::FastISel *X86::createFastISel(MachineFunction &mf,
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llvm::FastISel *X86::createFastISel(MachineFunction &mf,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const Value *, unsigned> &vm,
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