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A few 80 column fixes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-13 23:34:31 +00:00
parent 3a37866e53
commit 95369599c6
3 changed files with 5 additions and 5 deletions
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2
lib/Target/ARM/ARMFastISel.cpp
View File

@ -1292,7 +1292,7 @@ bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
// Finally update the result.
UpdateValueMap(I, ResultReg);
} else {
assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
EVT CopyVT = RVLocs[0].getValVT();
TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);

4
lib/Target/ARM/ARMInstrNEON.td
View File

@ -622,8 +622,8 @@ class VSTQQQQWBPseudo<InstrItinClass itin>
// VST1 : Vector Store (multiple single elements)
class VST1D<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST1,
"vst1", Dt, "\\{$src\\}, $addr", "", []>;
: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src),
IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>;
class VST1Q<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b1010,op7_4, (outs),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2,

4
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1207,7 +1207,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
let Inst{15-12} = 0b1111;
}
def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
"\t[$base, $a]", []> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
@ -1220,7 +1220,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
let Inst{5-4} = 0b00; // no shift is applied
}
def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
"\t[$base, $a, lsl $shamt]", []> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;