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A few 80 column fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1292,7 +1292,7 @@ bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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// Finally update the result.
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UpdateValueMap(I, ResultReg);
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} else {
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assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
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assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
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EVT CopyVT = RVLocs[0].getValVT();
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TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
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@ -622,8 +622,8 @@ class VSTQQQQWBPseudo<InstrItinClass itin>
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// VST1 : Vector Store (multiple single elements)
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class VST1D<bits<4> op7_4, string Dt>
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: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST1,
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"vst1", Dt, "\\{$src\\}, $addr", "", []>;
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: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src),
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IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>;
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class VST1Q<bits<4> op7_4, string Dt>
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: NLdSt<0,0b00,0b1010,op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2,
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@ -1207,7 +1207,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{15-12} = 0b1111;
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}
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def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
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def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
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"\t[$base, $a]", []> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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@ -1220,7 +1220,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{5-4} = 0b00; // no shift is applied
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}
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def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
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def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
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"\t[$base, $a, lsl $shamt]", []> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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