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Added i16 SH{L|R}D patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25468 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3068,12 +3068,22 @@ def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>;
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def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>;
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def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>;
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// (or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
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// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
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def : Pat<(or (srl R32:$src1, CL:$amt),
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(shl R32:$src2, (sub 32, CL:$amt))),
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(SHRD32rrCL R32:$src1, R32:$src2)>;
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// (or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
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// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
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def : Pat<(or (shl R32:$src1, CL:$amt),
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(srl R32:$src2, (sub 32, CL:$amt))),
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(SHLD32rrCL R32:$src1, R32:$src2)>;
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// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
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def : Pat<(or (srl R16:$src1, CL:$amt),
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(shl R16:$src2, (sub 16, CL:$amt))),
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(SHRD16rrCL R16:$src1, R16:$src2)>;
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// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
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def : Pat<(or (shl R16:$src1, CL:$amt),
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(srl R16:$src2, (sub 16, CL:$amt))),
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(SHLD16rrCL R16:$src1, R16:$src2)>;
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@ -48,7 +48,7 @@ namespace {
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cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
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cl::desc("Enable DAG-to-DAG isel for X86"),
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cl::location(X86DAGIsel),
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cl::init(false));
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cl::init(true));
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// FIXME: This should eventually be handled with target triples and
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// subtarget support!
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