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https://github.com/c64scene-ar/llvm-6502.git
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Remove some errant space charcters in mnemonic strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186932 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -343,7 +343,7 @@ def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmove\t{$op, %st(0)|ST(0), $op}">, DA;
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def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovu\t {$op, %st(0)|ST(0), $op}">, DA;
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"fcmovu\t{$op, %st(0)|ST(0), $op}">, DA;
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def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnb\t{$op, %st(0)|ST(0), $op}">, DB;
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def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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@ -6143,7 +6143,7 @@ let ExeDomain = SSEPackedSingle in {
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defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
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def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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"vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, OpSize, VEX;
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}
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defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
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@ -7266,62 +7266,62 @@ let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
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let Constraints = "$src1 = $dst" in {
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def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i8mem:$src2),
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"crc32{b} \t{$src2, $src1|$src1, $src2}",
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"crc32{b}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_8 GR32:$src1,
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(load addr:$src2)))]>;
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def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR8:$src2),
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"crc32{b} \t{$src2, $src1|$src1, $src2}",
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"crc32{b}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
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def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i16mem:$src2),
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"crc32{w} \t{$src2, $src1|$src1, $src2}",
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"crc32{w}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_16 GR32:$src1,
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(load addr:$src2)))]>,
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OpSize;
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def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR16:$src2),
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"crc32{w} \t{$src2, $src1|$src1, $src2}",
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"crc32{w}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
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OpSize;
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def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"crc32{l} \t{$src2, $src1|$src1, $src2}",
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"crc32{l}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_32 GR32:$src1,
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(load addr:$src2)))]>;
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def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR32:$src2),
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"crc32{l} \t{$src2, $src1|$src1, $src2}",
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"crc32{l}\t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
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def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i8mem:$src2),
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"crc32{b} \t{$src2, $src1|$src1, $src2}",
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"crc32{b}\t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64_8 GR64:$src1,
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(load addr:$src2)))]>,
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REX_W;
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def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR8:$src2),
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"crc32{b} \t{$src2, $src1|$src1, $src2}",
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"crc32{b}\t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
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REX_W;
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def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"crc32{q} \t{$src2, $src1|$src1, $src2}",
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"crc32{q}\t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64_64 GR64:$src1,
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(load addr:$src2)))]>,
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REX_W;
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def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"crc32{q} \t{$src2, $src1|$src1, $src2}",
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"crc32{q}\t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
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REX_W;
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