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[mips] [IAS] Outline NOP creation. NFC.
Summary: Make the code more readable by outlining NOP creation. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8320 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232371 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -193,6 +193,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -1367,22 +1370,11 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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}
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}
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// If this instruction has a delay slot and .set reorder is active,
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// emit a NOP after it.
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if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) {
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// If this instruction has a delay slot and .set reorder is active,
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// emit a NOP after it.
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Instructions.push_back(Inst);
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MCInst NopInst;
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if (hasShortDelaySlot(Inst.getOpcode())) {
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NopInst.setOpcode(Mips::MOVE16_MM);
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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} else {
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NopInst.setOpcode(Mips::SLL);
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateImm(0));
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}
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Instructions.push_back(NopInst);
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createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions);
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return false;
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}
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@ -1984,14 +1976,10 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(
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}
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Instructions.push_back(Inst);
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if (AssemblerOptions.back()->isReorder()) {
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// If .set reorder is active, emit a NOP after the branch instruction.
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MCInst NopInst;
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NopInst.setOpcode(Mips::MOVE16_MM);
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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Instructions.push_back(NopInst);
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}
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// If .set reorder is active, emit a NOP after the branch instruction.
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if (AssemblerOptions.back()->isReorder())
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createNop(true, IDLoc, Instructions);
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return false;
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}
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@ -2134,6 +2122,22 @@ MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst NopInst;
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if (hasShortDelaySlot) {
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NopInst.setOpcode(Mips::MOVE16_MM);
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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} else {
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NopInst.setOpcode(Mips::SLL);
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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NopInst.addOperand(MCOperand::CreateImm(0));
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}
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Instructions.push_back(NopInst);
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}
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unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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// As described by the Mips32r2 spec, the registers Rd and Rs for
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// jalr.hb must be different.
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