mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
Remove checks of getTypeAction from LegalizeOp; we already assert that
all results and all operands are legal, so this change shouldn't affect behavior at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72359 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
1fde9c5f77
commit
957bffaeca
@ -1334,19 +1334,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: {
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LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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if (Action == Legal && Tmp1 == Node->getOperand(0))
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if (Tmp1 == Node->getOperand(0))
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break;
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if (Action == Legal) {
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Tmp2 = Node->getOperand(1);
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Tmp3 = Node->getOperand(2);
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Tmp4 = Node->getOperand(3);
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} else {
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
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Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
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Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
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}
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
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break;
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}
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@ -1395,8 +1388,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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for (int x = 1; x < 6; ++x) {
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Ops[x] = Node->getOperand(x);
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if (!isTypeLegal(Ops[x].getValueType()))
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Ops[x] = PromoteOp(Ops[x]);
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}
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Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
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break;
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@ -1583,17 +1574,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// The type of the value to insert may not be legal, even though the vector
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// type is legal. Legalize/Promote accordingly. We do not handle Expand
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// here.
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switch (getTypeAction(Node->getOperand(1).getValueType())) {
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default: assert(0 && "Cannot expand insert element operand");
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case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
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case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
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case Expand:
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// FIXME: An alternative would be to check to see if the target is not
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// going to custom lower this operation, we could bitcast to half elt
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// width and perform two inserts at that width, if that is legal.
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Tmp2 = Node->getOperand(1);
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break;
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}
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Tmp2 = LegalizeOp(Node->getOperand(1));
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
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switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
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@ -1643,11 +1624,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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break;
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case ISD::SCALAR_TO_VECTOR:
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if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
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Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
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break;
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}
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Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
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Result = DAG.UpdateNodeOperands(Result, Tmp1);
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switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
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@ -2004,12 +1980,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Tmp1 = LegalizeOp(Tmp1);
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LastCALLSEQ_END = DAG.getEntryNode();
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switch (getTypeAction(Node->getOperand(1).getValueType())) {
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default: assert(0 && "Indirect target must be legal type (pointer)!");
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case Legal:
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
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break;
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}
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
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break;
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case ISD::BR_JT:
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@ -2063,23 +2034,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Tmp1 = LegalizeOp(Tmp1);
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LastCALLSEQ_END = DAG.getEntryNode();
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switch (getTypeAction(Node->getOperand(1).getValueType())) {
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case Expand: assert(0 && "It's impossible to expand bools");
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case Legal:
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
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break;
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case Promote: {
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Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
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// The top bits of the promoted condition are not necessarily zero, ensure
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// that the value is properly zero extended.
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unsigned BitWidth = Tmp2.getValueSizeInBits();
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if (!DAG.MaskedValueIsZero(Tmp2,
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APInt::getHighBitsSet(BitWidth, BitWidth-1)))
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Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
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break;
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}
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}
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// Basic block destination (Op#2) is always legal.
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
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@ -2396,9 +2351,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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case ISD::EXTRACT_ELEMENT: {
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MVT OpTy = Node->getOperand(0).getValueType();
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switch (getTypeAction(OpTy)) {
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default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
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case Legal:
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if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
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// 1 -> Hi
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Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
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@ -2411,23 +2363,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Node->getOperand(0));
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}
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break;
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case Expand:
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// Get both the low and high parts.
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ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
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if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
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Result = Tmp2; // 1 -> Hi
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else
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Result = Tmp1; // 0 -> Lo
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break;
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}
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break;
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}
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case ISD::CopyToReg:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
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"Register type must be legal!");
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// Legalize the incoming value (must be a legal type).
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Tmp2 = LegalizeOp(Node->getOperand(2));
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if (Node->getNumValues() == 1) {
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@ -2462,107 +2402,23 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case 3: // ret val
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Tmp2 = Node->getOperand(1);
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Tmp3 = Node->getOperand(2); // Signness
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switch (getTypeAction(Tmp2.getValueType())) {
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case Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
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break;
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case Expand:
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if (!Tmp2.getValueType().isVector()) {
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SDValue Lo, Hi;
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ExpandOp(Tmp2, Lo, Hi);
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// Big endian systems want the hi reg first.
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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if (Hi.getNode())
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Result = DAG.getNode(ISD::RET, dl, MVT::Other,
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Tmp1, Lo, Tmp3, Hi, Tmp3);
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else
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Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
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Result = LegalizeOp(Result);
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} else {
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SDNode *InVal = Tmp2.getNode();
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int InIx = Tmp2.getResNo();
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unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
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MVT EVT = InVal->getValueType(InIx).getVectorElementType();
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// Figure out if there is a simple type corresponding to this Vector
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// type. If so, convert to the vector type.
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MVT TVT = MVT::getVectorVT(EVT, NumElems);
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if (TLI.isTypeLegal(TVT)) {
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// Turn this into a return of the vector type.
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Tmp2 = LegalizeOp(Tmp2);
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
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} else if (NumElems == 1) {
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// Turn this into a return of the scalar type.
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Tmp2 = ScalarizeVectorOp(Tmp2);
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Tmp2 = LegalizeOp(Tmp2);
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
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// FIXME: Returns of gcc generic vectors smaller than a legal type
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// should be returned in integer registers!
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// The scalarized value type may not be legal, e.g. it might require
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// promotion or expansion. Relegalize the return.
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Result = LegalizeOp(Result);
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} else {
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// FIXME: Returns of gcc generic vectors larger than a legal vector
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// type should be returned by reference!
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SDValue Lo, Hi;
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SplitVectorOp(Tmp2, Lo, Hi);
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Result = DAG.getNode(ISD::RET, dl, MVT::Other,
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Tmp1, Lo, Tmp3, Hi, Tmp3);
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Result = LegalizeOp(Result);
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}
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}
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break;
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case Promote:
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Tmp2 = PromoteOp(Node->getOperand(1));
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
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Result = LegalizeOp(Result);
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break;
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}
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break;
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case 1: // ret void
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Result = DAG.UpdateNodeOperands(Result, Tmp1);
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break;
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default: { // ret <values>
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SmallVector<SDValue, 8> NewValues;
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NewValues.push_back(Tmp1);
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for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
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switch (getTypeAction(Node->getOperand(i).getValueType())) {
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case Legal:
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for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
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NewValues.push_back(LegalizeOp(Node->getOperand(i)));
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NewValues.push_back(Node->getOperand(i+1));
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break;
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case Expand: {
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SDValue Lo, Hi;
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assert(!Node->getOperand(i).getValueType().isExtended() &&
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"FIXME: TODO: implement returning non-legal vector types!");
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ExpandOp(Node->getOperand(i), Lo, Hi);
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NewValues.push_back(Lo);
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NewValues.push_back(Node->getOperand(i+1));
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if (Hi.getNode()) {
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NewValues.push_back(Hi);
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NewValues.push_back(Node->getOperand(i+1));
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}
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break;
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}
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case Promote:
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assert(0 && "Can't promote multiple return value yet!");
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}
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if (NewValues.size() == Node->getNumOperands())
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Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
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else
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Result = DAG.getNode(ISD::RET, dl, MVT::Other,
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&NewValues[0], NewValues.size());
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break;
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}
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}
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if (Result.getOpcode() == ISD::RET) {
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switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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@ -2571,7 +2427,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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if (Tmp1.getNode()) Result = Tmp1;
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break;
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}
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}
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break;
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case ISD::STORE: {
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StoreSDNode *ST = cast<StoreSDNode>(Node);
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@ -2628,8 +2483,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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}
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switch (getTypeAction(ST->getMemoryVT())) {
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case Legal: {
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{
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Tmp3 = LegalizeOp(ST->getValue());
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
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ST->getOffset());
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@ -2663,111 +2517,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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break;
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}
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case Promote:
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if (!ST->getMemoryVT().isVector()) {
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// Truncate the value and store the result.
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Tmp3 = PromoteOp(ST->getValue());
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Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
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SVOffset, ST->getMemoryVT(),
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isVolatile, Alignment);
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break;
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}
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// Fall thru to expand for vector
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case Expand: {
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unsigned IncrementSize = 0;
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SDValue Lo, Hi;
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// If this is a vector type, then we have to calculate the increment as
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// the product of the element size in bytes, and the number of elements
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// in the high half of the vector.
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if (ST->getValue().getValueType().isVector()) {
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SDNode *InVal = ST->getValue().getNode();
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int InIx = ST->getValue().getResNo();
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MVT InVT = InVal->getValueType(InIx);
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unsigned NumElems = InVT.getVectorNumElements();
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MVT EVT = InVT.getVectorElementType();
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// Figure out if there is a simple type corresponding to this Vector
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// type. If so, convert to the vector type.
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MVT TVT = MVT::getVectorVT(EVT, NumElems);
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if (TLI.isTypeLegal(TVT)) {
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// Turn this into a normal store of the vector type.
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} else {
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Tmp3 = LegalizeOp(ST->getValue());
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Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
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SVOffset, isVolatile, Alignment);
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Result = LegalizeOp(Result);
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break;
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} else if (NumElems == 1) {
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// Turn this into a normal store of the scalar type.
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Tmp3 = ScalarizeVectorOp(ST->getValue());
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Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
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SVOffset, isVolatile, Alignment);
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// The scalarized value type may not be legal, e.g. it might require
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// promotion or expansion. Relegalize the scalar store.
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Result = LegalizeOp(Result);
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break;
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} else {
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// Check if we have widen this node with another value
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std::map<SDValue, SDValue>::iterator I =
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WidenNodes.find(ST->getValue());
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if (I != WidenNodes.end()) {
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Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
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break;
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}
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else {
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SplitVectorOp(ST->getValue(), Lo, Hi);
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IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
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EVT.getSizeInBits()/8;
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}
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}
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} else {
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ExpandOp(ST->getValue(), Lo, Hi);
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IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
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if (Hi.getNode() && TLI.isBigEndian())
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std::swap(Lo, Hi);
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}
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Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
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SVOffset, isVolatile, Alignment);
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if (Hi.getNode() == NULL) {
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// Must be int <-> float one-to-one expansion.
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Result = Lo;
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break;
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}
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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assert(isTypeLegal(Tmp2.getValueType()) &&
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"Pointers must be legal!");
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SVOffset += IncrementSize;
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Alignment = MinAlign(Alignment, IncrementSize);
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Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
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SVOffset, isVolatile, Alignment);
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
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break;
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} // case Expand
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}
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} else {
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switch (getTypeAction(ST->getValue().getValueType())) {
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case Legal:
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Tmp3 = LegalizeOp(ST->getValue());
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break;
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case Promote:
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if (!ST->getValue().getValueType().isVector()) {
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// We can promote the value, the truncstore will still take care of it.
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Tmp3 = PromoteOp(ST->getValue());
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break;
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}
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// Vector case falls through to expand
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case Expand:
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// Just store the low part. This may become a non-trunc store, so make
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// sure to use getTruncStore, not UpdateNodeOperands below.
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ExpandOp(ST->getValue(), Tmp3, Tmp4);
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return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
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SVOffset, MVT::i8, isVolatile, Alignment);
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}
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MVT StVT = ST->getMemoryVT();
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unsigned StWidth = StVT.getSizeInBits();
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@ -2953,22 +2704,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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return Result;
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case ISD::SELECT:
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "It's impossible to expand bools");
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case Legal:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
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break;
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case Promote: {
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assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
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Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
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// Make sure the condition is either zero or one.
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unsigned BitWidth = Tmp1.getValueSizeInBits();
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if (!DAG.MaskedValueIsZero(Tmp1,
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APInt::getHighBitsSet(BitWidth, BitWidth-1)))
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Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
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break;
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}
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}
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Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
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Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
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@ -3231,15 +2967,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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!Node->getValueType(0).isVector())
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Tmp2 = DAG.getShiftAmountOperand(Tmp2);
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switch (getTypeAction(Tmp2.getValueType())) {
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case Expand: assert(0 && "Not possible");
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case Legal:
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Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
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break;
|
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case Promote:
|
||||
Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
|
||||
break;
|
||||
}
|
||||
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
|
||||
|
||||
@ -3402,15 +3130,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
|
||||
case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
|
||||
switch (getTypeAction(Node->getOperand(1).getValueType())) {
|
||||
case Expand: assert(0 && "Not possible");
|
||||
case Legal:
|
||||
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
|
||||
break;
|
||||
case Promote:
|
||||
Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
|
||||
break;
|
||||
}
|
||||
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
|
||||
|
||||
@ -4014,9 +3734,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
SDValue STyOp = Node->getOperand(2);
|
||||
SDValue RndOp = Node->getOperand(3);
|
||||
SDValue SatOp = Node->getOperand(4);
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
|
||||
RndOp, SatOp);
|
||||
@ -4026,15 +3743,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
if (Tmp1.getNode()) Result = Tmp1;
|
||||
}
|
||||
break;
|
||||
case Promote:
|
||||
Result = PromoteOp(Node->getOperand(0));
|
||||
// For FP, make Op1 a i32
|
||||
|
||||
Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
|
||||
DTyOp, STyOp, RndOp, SatOp, CvtCode);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
} // end switch CvtCode
|
||||
break;
|
||||
@ -4048,8 +3756,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
break;
|
||||
}
|
||||
case ISD::TRUNCATE:
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
|
||||
default: assert(0 && "Unknown TRUNCATE legalization operation action!");
|
||||
@ -4067,26 +3773,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
assert(Result.getValueType().isVector() && "must be vector type");
|
||||
// Unroll the truncate. We should do better.
|
||||
Result = LegalizeOp(UnrollVectorOp(Result));
|
||||
}
|
||||
break;
|
||||
case Expand:
|
||||
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
|
||||
|
||||
// Since the result is legal, we should just be able to truncate the low
|
||||
// part of the source.
|
||||
Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
|
||||
break;
|
||||
case Promote:
|
||||
Result = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ISD::FP_TO_SINT:
|
||||
case ISD::FP_TO_UINT:
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
|
||||
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
|
||||
@ -4126,58 +3818,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
False = DAG.getNode(ISD::XOR, dl, NVT, False,
|
||||
DAG.getConstant(x, NVT));
|
||||
Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
|
||||
break;
|
||||
} else {
|
||||
assert(0 && "Do not know how to expand FP_TO_SINT yet!");
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case Expand: {
|
||||
MVT VT = Op.getValueType();
|
||||
MVT OVT = Node->getOperand(0).getValueType();
|
||||
// Convert ppcf128 to i32
|
||||
if (OVT == MVT::ppcf128 && VT == MVT::i32) {
|
||||
if (Node->getOpcode() == ISD::FP_TO_SINT) {
|
||||
Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
|
||||
Node->getOperand(0), DAG.getValueType(MVT::f64));
|
||||
Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
|
||||
DAG.getIntPtrConstant(1));
|
||||
Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
|
||||
} else {
|
||||
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
|
||||
APFloat apf = APFloat(APInt(128, 2, TwoE31));
|
||||
Tmp2 = DAG.getConstantFP(apf, OVT);
|
||||
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
|
||||
// FIXME: generated code sucks.
|
||||
Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
|
||||
Tmp2,
|
||||
DAG.getNode(ISD::ADD, dl, MVT::i32,
|
||||
DAG.getNode(ISD::FP_TO_SINT, dl, VT,
|
||||
DAG.getNode(ISD::FSUB, dl, OVT,
|
||||
Node->getOperand(0), Tmp2)),
|
||||
DAG.getConstant(0x80000000, MVT::i32)),
|
||||
DAG.getNode(ISD::FP_TO_SINT, dl, VT,
|
||||
Node->getOperand(0)),
|
||||
DAG.getCondCode(ISD::SETGE));
|
||||
}
|
||||
break;
|
||||
}
|
||||
// Convert f32 / f64 to i32 / i64 / i128.
|
||||
RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
|
||||
RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
|
||||
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
|
||||
SDValue Dummy;
|
||||
Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
|
||||
break;
|
||||
}
|
||||
case Promote:
|
||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
|
||||
Result = LegalizeOp(Result);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ISD::FP_EXTEND: {
|
||||
MVT DstVT = Op.getValueType();
|
||||
@ -4188,18 +3834,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
|
||||
break;
|
||||
}
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1);
|
||||
break;
|
||||
case Promote:
|
||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ISD::FP_ROUND: {
|
||||
MVT DstVT = Op.getValueType();
|
||||
@ -4214,26 +3851,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
|
||||
break;
|
||||
}
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
|
||||
break;
|
||||
case Promote:
|
||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
|
||||
Node->getOperand(1));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ISD::ANY_EXTEND:
|
||||
case ISD::ZERO_EXTEND:
|
||||
case ISD::SIGN_EXTEND:
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
||||
case Legal:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1);
|
||||
if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
|
||||
@ -4242,28 +3866,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
if (Tmp1.getNode()) Result = Tmp1;
|
||||
}
|
||||
break;
|
||||
case Promote:
|
||||
switch (Node->getOpcode()) {
|
||||
case ISD::ANY_EXTEND:
|
||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
|
||||
break;
|
||||
case ISD::ZERO_EXTEND:
|
||||
Result = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
|
||||
Result = DAG.getZeroExtendInReg(Result, dl,
|
||||
Node->getOperand(0).getValueType());
|
||||
break;
|
||||
case ISD::SIGN_EXTEND:
|
||||
Result = PromoteOp(Node->getOperand(0));
|
||||
Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
|
||||
Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
|
||||
Result,
|
||||
DAG.getValueType(Node->getOperand(0).getValueType()));
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ISD::FP_ROUND_INREG:
|
||||
case ISD::SIGN_EXTEND_INREG: {
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user