6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-21 01:25:20 +00:00
Code Issues Projects Releases Wiki Activity

Implement setcc correctly for G5 and non-G5 systems

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-25 21:39:42 +00:00
parent 64906a06b3
commit 957fcfbd89
1 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -1087,17 +1087,23 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
SDOperand CCReg =
SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC);
SDOperand IntCR;
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) {
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CCReg);
} else {
assert(0 && "Not imp yet!");
// FIXME: HOW DO WE DO THIS??
#if 0
//SDOperand CR7Op = CurDAG->getCopyToReg();
BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
BuildMI(BB, PPC::MFCR, 0, IntCR);
#endif
}
// Force the ccreg into CR7.
SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::Other);
VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
std::vector<SDOperand> Ops;
Ops.push_back(CurDAG->getEntryNode());
Ops.push_back(CR7Reg);
Ops.push_back(CCReg);
CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
else
IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
if (!Inv) {
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, IntCR,