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Use xorl instead of xorq to enter a zero into a 64-bit register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2007-09-17 14:55:08 +00:00
parent 5f6913cecd
commit 959062475d
1 changed files with 4 additions and 2 deletions
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6
lib/Target/X86/X86InstrX86-64.td
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@ -1018,13 +1018,15 @@ def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
[(set GR64:$dst, (zextloadi64i32 addr:$src))]>; [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
// Alias instructions that map movr0 to xor. // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
// equivalent due to implicit zero-extending, and it sometimes has a smaller
// encoding.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok. // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
// FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
// when we have a better way to specify isel priority. // when we have a better way to specify isel priority.
let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in
def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins), def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
"xor{q}\t$dst, $dst", "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
[(set GR64:$dst, 0)]>; [(set GR64:$dst, 0)]>;
// Materialize i64 constant where top 32-bits are zero. // Materialize i64 constant where top 32-bits are zero.