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Revert r57699. It's causing regressions in
test/CodeGen/X86/2008-09-17-inline-asm-1.ll and a few others, and it breaks the llvm-gcc build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57747 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4667,7 +4667,6 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
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break;
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}
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// The return value of the call is this value. As such, there is no
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// corresponding argument.
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assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
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@ -4700,30 +4699,6 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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}
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OpInfo.ConstraintVT = OpVT;
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}
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// Second pass over the constraints: compute which constraint option to use
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// and assign registers to constraints that want a specific physreg.
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for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
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SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
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// If this is an output operand with a matching input operand, look up the
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// matching input. It might have a different type (e.g. the output might be
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// i32 and the input i64) and we need to pick the larger width to ensure we
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// reserve the right number of registers.
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if (OpInfo.hasMatchingInput()) {
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SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
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if (OpInfo.ConstraintVT != Input.ConstraintVT) {
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assert(OpInfo.ConstraintVT.isInteger() &&
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Input.ConstraintVT.isInteger() &&
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"Asm constraints must be the same or different sized integers");
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if (OpInfo.ConstraintVT.getSizeInBits() <
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Input.ConstraintVT.getSizeInBits())
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OpInfo.ConstraintVT = Input.ConstraintVT;
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else
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Input.ConstraintVT = OpInfo.ConstraintVT;
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}
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}
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// Compute the constraint code and ConstraintType to use.
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TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
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@ -4973,26 +4948,24 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// and set it as the value of the call.
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if (!RetValRegs.Regs.empty()) {
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SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
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MVT ResultType = TLI.getValueType(CS.getType());
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// If any of the results of the inline asm is a vector, it may have the
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// wrong width/num elts. This can happen for register classes that can
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// contain multiple different value types. The preg or vreg allocated may
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// not have the same VT as was expected. Convert it to the right type
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// with bit_convert.
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// FIXME: Is this sufficient for inline asms with MRVs?
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if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
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Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val);
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} else if (ResultType != Val.getValueType() &&
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ResultType.isInteger() && Val.getValueType().isInteger()) {
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// If a result value was tied to an input value, the computed result may
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// have a wider width than the expected result. Extract the relevant
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// portion.
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Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val);
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// not have the same VT as was expected. Convert it to the right type with
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// bit_convert.
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if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
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for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
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if (Val.getNode()->getValueType(i).isVector())
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Val = DAG.getNode(ISD::BIT_CONVERT,
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TLI.getValueType(ResSTy->getElementType(i)), Val);
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}
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} else {
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if (Val.getValueType().isVector())
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Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
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Val);
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}
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assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
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setValue(CS.getInstruction(), Val);
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}
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@ -5246,8 +5219,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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Value != NumValues; ++Value) {
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MVT VT = ValueVTs[Value];
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const Type *ArgTy = VT.getTypeForMVT();
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SDValue Op = SDValue(Args[i].Node.getNode(),
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Args[i].Node.getResNo() + Value);
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SDValue Op = SDValue(Args[i].Node.getNode(), Args[i].Node.getResNo() + Value);
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ISD::ArgFlagsTy Flags;
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unsigned OriginalAlignment =
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getTargetData()->getABITypeAlignment(ArgTy);
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@ -1,11 +0,0 @@
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; RUN: llvm-as < %s | llc
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; PR2356
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
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target triple = "powerpc-apple-darwin9"
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define i32 @test(i64 %x, i32* %p) nounwind {
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entry:
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%asmtmp = call i32 asm "", "=r,0"(i64 0) nounwind ; <i32> [#uses=0]
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%y = add i32 %asmtmp, 1
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ret i32 %y
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}
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