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https://github.com/c64scene-ar/llvm-6502.git
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remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -83,7 +83,7 @@ public:
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RegSet.insert(*I);
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RegSet.insert(*I);
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}
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}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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virtual ~TargetRegisterClass() {} // Allow subclasses
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/// getID() - Return the register class ID number.
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/// getID() - Return the register class ID number.
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///
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///
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unsigned getID() const { return ID; }
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unsigned getID() const { return ID; }
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@ -122,7 +122,7 @@ public:
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return true;
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return true;
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return false;
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return false;
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}
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}
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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vt_iterator vt_begin() const {
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@ -172,7 +172,7 @@ public:
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/// hasSubClass - return true if the the specified TargetRegisterClass
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/// hasSubClass - return true if the the specified TargetRegisterClass
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/// is a proper subset of this TargetRegisterClass.
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/// is a proper subset of this TargetRegisterClass.
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bool hasSubClass(const TargetRegisterClass *cs) const {
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bool hasSubClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubClasses[i] != NULL; ++i)
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for (int i = 0; SubClasses[i] != NULL; ++i)
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if (SubClasses[i] == cs)
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if (SubClasses[i] == cs)
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return true;
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return true;
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return false;
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return false;
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@ -183,17 +183,17 @@ public:
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sc_iterator subclasses_begin() const {
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sc_iterator subclasses_begin() const {
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return SubClasses;
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return SubClasses;
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}
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}
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sc_iterator subclasses_end() const {
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sc_iterator subclasses_end() const {
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sc_iterator I = SubClasses;
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sc_iterator I = SubClasses;
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while (*I != NULL) ++I;
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while (*I != NULL) ++I;
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return I;
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return I;
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}
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}
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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/// proper superset of this TargetRegisterClass.
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/// proper superset of this TargetRegisterClass.
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bool hasSuperClass(const TargetRegisterClass *cs) const {
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bool hasSuperClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SuperClasses[i] != NULL; ++i)
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for (int i = 0; SuperClasses[i] != NULL; ++i)
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if (SuperClasses[i] == cs)
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if (SuperClasses[i] == cs)
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return true;
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return true;
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return false;
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return false;
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@ -204,7 +204,7 @@ public:
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sc_iterator superclasses_begin() const {
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sc_iterator superclasses_begin() const {
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return SuperClasses;
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return SuperClasses;
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}
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}
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sc_iterator superclasses_end() const {
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sc_iterator superclasses_end() const {
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sc_iterator I = SuperClasses;
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sc_iterator I = SuperClasses;
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while (*I != NULL) ++I;
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while (*I != NULL) ++I;
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@ -216,7 +216,7 @@ public:
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bool isASubClass() const {
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bool isASubClass() const {
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return SuperClasses[0] != 0;
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return SuperClasses[0] != 0;
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}
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// allocate, and the preferred order to allocate them in. For example,
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@ -413,11 +413,11 @@ public:
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SubregHash[index*2+1] != 0) {
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SubregHash[index*2+1] != 0) {
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if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
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if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
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return true;
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return true;
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index = (index + ProbeAmt) & (SubregHashSize-1);
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index = (index + ProbeAmt) & (SubregHashSize-1);
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ProbeAmt += 2;
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ProbeAmt += 2;
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}
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}
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return false;
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return false;
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}
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}
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@ -431,11 +431,11 @@ public:
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SuperregHash[index*2+1] != 0) {
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SuperregHash[index*2+1] != 0) {
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if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
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if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
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return true;
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return true;
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index = (index + ProbeAmt) & (SuperregHashSize-1);
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index = (index + ProbeAmt) & (SuperregHashSize-1);
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ProbeAmt += 2;
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ProbeAmt += 2;
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}
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}
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return false;
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return false;
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}
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}
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@ -465,7 +465,7 @@ public:
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterClass *RC) const {
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const TargetRegisterClass *RC) const {
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for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
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for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
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if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
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if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
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@ -494,7 +494,7 @@ public:
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unsigned getNumRegClasses() const {
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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return (unsigned)(regclass_end()-regclass_begin());
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}
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class TargetOperandInfo.
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/// value. See class TargetOperandInfo.
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const TargetRegisterClass *getRegClass(unsigned i) const {
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const TargetRegisterClass *getRegClass(unsigned i) const {
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@ -560,7 +560,7 @@ public:
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
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return false;
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return false;
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}
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}
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/// hasFP - Return true if the specified function should have a dedicated
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/// hasFP - Return true if the specified function should have a dedicated
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/// frame pointer register. For most targets this is true only if the function
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/// frame pointer register. For most targets this is true only if the function
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/// has variable sized allocas or if frame pointer elimination is disabled.
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/// has variable sized allocas or if frame pointer elimination is disabled.
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@ -650,10 +650,10 @@ public:
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virtual void emitPrologue(MachineFunction &MF) const = 0;
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virtual void emitPrologue(MachineFunction &MF) const = 0;
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virtual void emitEpilogue(MachineFunction &MF,
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virtual void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const = 0;
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MachineBasicBlock &MBB) const = 0;
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// Debug information queries.
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/// Debug information queries.
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// number. Returns -1 if there is no equivalent value. The second
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/// number. Returns -1 if there is no equivalent value. The second
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/// parameter allows targets to use different numberings for EH info and
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/// parameter allows targets to use different numberings for EH info and
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@ -667,11 +667,11 @@ public:
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/// getFrameIndexOffset - Returns the displacement from the frame register to
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/// getFrameIndexOffset - Returns the displacement from the frame register to
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/// the stack frame of the specified index.
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/// the stack frame of the specified index.
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virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
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virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
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/// getRARegister - This method should return the register where the return
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/// getRARegister - This method should return the register where the return
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/// address can be found.
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/// address can be found.
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virtual unsigned getRARegister() const = 0;
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virtual unsigned getRARegister() const = 0;
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/// getInitialFrameState - Returns a list of machine moves that are assumed
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/// getInitialFrameState - Returns a list of machine moves that are assumed
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/// on entry to all functions. Note that LabelID is ignored (assumed to be
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/// on entry to all functions. Note that LabelID is ignored (assumed to be
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/// the beginning of the function.)
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/// the beginning of the function.)
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