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https://github.com/c64scene-ar/llvm-6502.git
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Switch TargetRegisterInfo::getSubReg() to use a lookup table.
Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -735,28 +735,44 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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// Emit the data table for getSubReg().
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if (SubRegIndices.size()) {
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OS << "static const unsigned short " << TargetName << "SubRegTable[]["
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<< SubRegIndices.size() << "] = {\n";
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
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OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
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if (SRM.empty()) {
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OS << " {0},\n";
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continue;
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}
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OS << " {";
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for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
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// FIXME: We really should keep this to 80 columns...
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CodeGenRegister::SubRegMap::const_iterator SubReg =
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SRM.find(SubRegIndices[j]);
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if (SubReg != SRM.end())
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OS << getQualifiedName(SubReg->second->TheDef);
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else
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OS << "0";
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if (j != je - 1)
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OS << ", ";
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}
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OS << "}" << (i != e ? "," : "") << "\n";
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}
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OS << "};\n\n";
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}
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// Emit the subregister + index mapping function based on the information
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// Emit the subregister + index mapping function based on the information
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// calculated above.
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// calculated above.
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OS << "unsigned " << ClassName
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OS << "unsigned " << ClassName
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<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
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<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
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<< " switch (RegNo) {\n"
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<< " assert(RegNo > 0 && Index > 0 && \"invalid subreg query!\");\n";
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<< " default:\n return 0;\n";
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if (SubRegIndices.size())
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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OS << " return " << TargetName << "SubRegTable[RegNo - 1][Index - 1];\n"
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const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
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<< "}\n\n";
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if (SRM.empty())
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else
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continue;
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OS << " return 0;\n}\n\n";
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OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
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OS << " switch (Index) {\n";
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OS << " default: return 0;\n";
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for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
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ie = SRM.end(); ii != ie; ++ii)
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OS << " case " << ii->first->getQualifiedName()
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<< ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
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OS << " };\n" << " break;\n";
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}
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OS << " };\n";
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OS << " return 0;\n";
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OS << "}\n\n";
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OS << "unsigned " << ClassName
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OS << "unsigned " << ClassName
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<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
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<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
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