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Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -24,7 +24,8 @@ namespace llvm {
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class APInt;
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class TargetData;
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class StringRef;
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class MDNode;
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/// ComputeMaskedBits - Determine which of the bits specified in Mask are
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/// known to be either zero or one and return them in the KnownZero/KnownOne
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/// bit sets. This code only analyzes bits in Mask, in order to short-circuit
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@ -38,7 +39,9 @@ namespace llvm {
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void ComputeMaskedBits(Value *V, const APInt &Mask, APInt &KnownZero,
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APInt &KnownOne, const TargetData *TD = 0,
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unsigned Depth = 0);
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void computeMaskedBitsLoad(const MDNode &Ranges, const APInt &Mask,
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APInt &KnownZero);
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/// ComputeSignBit - Determine whether the sign bit is known to be zero or
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/// one. Convenience wrapper around ComputeMaskedBits.
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void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
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@ -380,7 +380,8 @@ public:
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MachineMemOperand *getMachineMemOperand(MachinePointerInfo PtrInfo,
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unsigned f, uint64_t s,
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unsigned base_alignment,
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const MDNode *TBAAInfo = 0);
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const MDNode *TBAAInfo = 0,
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const MDNode *Ranges = 0);
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/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
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/// an existing one, adjusting by an offset and using the given size.
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@ -84,6 +84,7 @@ class MachineMemOperand {
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uint64_t Size;
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unsigned Flags;
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const MDNode *TBAAInfo;
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const MDNode *Ranges;
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public:
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/// Flags values. These may be or'd together.
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@ -105,7 +106,8 @@ public:
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/// MachineMemOperand - Construct an MachineMemOperand object with the
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/// specified PtrInfo, flags, size, and base alignment.
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MachineMemOperand(MachinePointerInfo PtrInfo, unsigned flags, uint64_t s,
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unsigned base_alignment, const MDNode *TBAAInfo = 0);
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unsigned base_alignment, const MDNode *TBAAInfo = 0,
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const MDNode *Ranges = 0);
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const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
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@ -140,6 +142,9 @@ public:
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/// getTBAAInfo - Return the TBAA tag for the memory reference.
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const MDNode *getTBAAInfo() const { return TBAAInfo; }
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/// getRanges - Return the range tag for the memory reference.
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const MDNode *getRanges() const { return Ranges; }
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bool isLoad() const { return Flags & MOLoad; }
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bool isStore() const { return Flags & MOStore; }
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bool isVolatile() const { return Flags & MOVolatile; }
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@ -654,7 +654,7 @@ public:
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SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
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MachinePointerInfo PtrInfo, bool isVolatile,
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bool isNonTemporal, bool isInvariant, unsigned Alignment,
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const MDNode *TBAAInfo = 0);
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const MDNode *TBAAInfo = 0, const MDNode *Ranges = 0);
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SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
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SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
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EVT MemVT, bool isVolatile,
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@ -667,7 +667,8 @@ public:
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SDValue Chain, SDValue Ptr, SDValue Offset,
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MachinePointerInfo PtrInfo, EVT MemVT,
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bool isVolatile, bool isNonTemporal, bool isInvariant,
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unsigned Alignment, const MDNode *TBAAInfo = 0);
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unsigned Alignment, const MDNode *TBAAInfo = 0,
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const MDNode *Ranges = 0);
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SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
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EVT VT, DebugLoc dl,
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SDValue Chain, SDValue Ptr, SDValue Offset,
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@ -933,6 +933,9 @@ public:
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/// Returns the TBAAInfo that describes the dereference.
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const MDNode *getTBAAInfo() const { return MMO->getTBAAInfo(); }
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/// Returns the Ranges that describes the dereference.
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const MDNode *getRanges() const { return MMO->getRanges(); }
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/// getMemoryVT - Return the type of the in-memory value.
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EVT getMemoryVT() const { return MemoryVT; }
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@ -197,8 +197,8 @@ static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
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KnownOne.setBit(BitWidth - 1);
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}
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static void computeMaskedBitsLoad(const MDNode &Ranges, const APInt &Mask,
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APInt &KnownZero) {
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void llvm::computeMaskedBitsLoad(const MDNode &Ranges, const APInt &Mask,
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APInt &KnownZero) {
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unsigned BitWidth = Mask.getBitWidth();
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unsigned NumRanges = Ranges.getNumOperands() / 2;
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assert(NumRanges >= 1);
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@ -195,9 +195,10 @@ MachineFunction::DeleteMachineBasicBlock(MachineBasicBlock *MBB) {
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MachineMemOperand *
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MachineFunction::getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f,
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uint64_t s, unsigned base_alignment,
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const MDNode *TBAAInfo) {
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const MDNode *TBAAInfo,
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const MDNode *Ranges) {
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return new (Allocator) MachineMemOperand(PtrInfo, f, s, base_alignment,
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TBAAInfo);
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TBAAInfo, Ranges);
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}
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MachineMemOperand *
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@ -381,10 +381,11 @@ MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
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MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
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uint64_t s, unsigned int a,
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const MDNode *TBAAInfo)
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const MDNode *TBAAInfo,
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const MDNode *Ranges)
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: PtrInfo(ptrinfo), Size(s),
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Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
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TBAAInfo(TBAAInfo) {
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TBAAInfo(TBAAInfo), Ranges(Ranges) {
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assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
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"invalid pointer value");
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assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
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@ -1889,11 +1889,13 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
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return;
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}
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case ISD::LOAD: {
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LoadSDNode *LD = cast<LoadSDNode>(Op);
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if (ISD::isZEXTLoad(Op.getNode())) {
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LoadSDNode *LD = cast<LoadSDNode>(Op);
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EVT VT = LD->getMemoryVT();
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unsigned MemBits = VT.getScalarType().getSizeInBits();
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KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
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} else if (const MDNode *Ranges = LD->getRanges()) {
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computeMaskedBitsLoad(*Ranges, Mask, KnownZero);
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}
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return;
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}
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@ -4170,7 +4172,8 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
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SDValue Ptr, SDValue Offset,
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MachinePointerInfo PtrInfo, EVT MemVT,
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bool isVolatile, bool isNonTemporal, bool isInvariant,
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unsigned Alignment, const MDNode *TBAAInfo) {
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unsigned Alignment, const MDNode *TBAAInfo,
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const MDNode *Ranges) {
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assert(Chain.getValueType() == MVT::Other &&
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"Invalid chain type");
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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@ -4192,7 +4195,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
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MachineFunction &MF = getMachineFunction();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment,
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TBAAInfo);
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TBAAInfo, Ranges);
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return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
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}
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@ -4248,11 +4251,12 @@ SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
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MachinePointerInfo PtrInfo,
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bool isVolatile, bool isNonTemporal,
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bool isInvariant, unsigned Alignment,
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const MDNode *TBAAInfo) {
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const MDNode *TBAAInfo,
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const MDNode *Ranges) {
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SDValue Undef = getUNDEF(Ptr.getValueType());
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return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
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PtrInfo, VT, isVolatile, isNonTemporal, isInvariant, Alignment,
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TBAAInfo);
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PtrInfo, VT, isVolatile, isNonTemporal, isInvariant, Alignment,
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TBAAInfo, Ranges);
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}
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SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
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@ -3215,6 +3215,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
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bool isInvariant = I.getMetadata("invariant.load") != 0;
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unsigned Alignment = I.getAlignment();
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const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
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const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<uint64_t, 4> Offsets;
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@ -3262,7 +3263,8 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
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DAG.getConstant(Offsets[i], PtrVT));
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SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
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A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
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isNonTemporal, isInvariant, Alignment, TBAAInfo);
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isNonTemporal, isInvariant, Alignment, TBAAInfo,
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Ranges);
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Values[i] = L;
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Chains[ChainI] = L.getValue(1);
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14
test/CodeGen/X86/pr12360.ll
Normal file
14
test/CodeGen/X86/pr12360.ll
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@ -0,0 +1,14 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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define zeroext i1 @f1(i8* %x) {
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entry:
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%0 = load i8* %x, align 1, !range !0
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%tobool = trunc i8 %0 to i1
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ret i1 %tobool
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}
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; CHECK: f1:
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; CHECK: movb (%rdi), %al
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; CHECK-NEXT: ret
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!0 = metadata !{i8 0, i8 2}
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