mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish instructions to access odd numbered registers (instead of "a" and "b"). No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
00bf1d93d7
commit
95ffecd4fe
@ -1859,37 +1859,45 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case Intrinsic::arm_neon_vld3: {
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unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
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ARM::VLD3d32, ARM::VLD3d64 };
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unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
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unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
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unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
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ARM::VLD3q16_UPD,
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ARM::VLD3q32_UPD };
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unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
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ARM::VLD3q16odd_UPD,
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ARM::VLD3q32odd_UPD };
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return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld4: {
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unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
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ARM::VLD4d32, ARM::VLD4d64 };
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unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
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unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
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unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
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ARM::VLD4q16_UPD,
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ARM::VLD4q32_UPD };
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unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
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ARM::VLD4q16odd_UPD,
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ARM::VLD4q32odd_UPD };
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return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld2lane: {
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unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
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unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
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unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
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unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
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unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
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return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld3lane: {
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unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
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unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
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unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
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unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
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unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
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return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld4lane: {
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unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
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unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
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unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
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unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
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unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
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return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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@ -1903,37 +1911,45 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case Intrinsic::arm_neon_vst3: {
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unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
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ARM::VST3d32, ARM::VST3d64 };
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unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
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unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
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unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
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ARM::VST3q16_UPD,
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ARM::VST3q32_UPD };
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unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD,
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ARM::VST3q16odd_UPD,
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ARM::VST3q32odd_UPD };
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return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst4: {
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unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
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ARM::VST4d32, ARM::VST4d64 };
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unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
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unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
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unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
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ARM::VST4q16_UPD,
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ARM::VST4q32_UPD };
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unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
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ARM::VST4q16odd_UPD,
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ARM::VST4q32odd_UPD };
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return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst2lane: {
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unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
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unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
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unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
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unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
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unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
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return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst3lane: {
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unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
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unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
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unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
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unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
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unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
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return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst4lane: {
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unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
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unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
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unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
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unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
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unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
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return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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}
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@ -283,14 +283,14 @@ def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
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def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
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// vld3 to double-spaced even registers.
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def VLD3q8a : VLD3WB<0b0000, "8">;
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def VLD3q16a : VLD3WB<0b0100, "16">;
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def VLD3q32a : VLD3WB<0b1000, "32">;
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def VLD3q8_UPD : VLD3WB<0b0000, "8">;
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def VLD3q16_UPD : VLD3WB<0b0100, "16">;
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def VLD3q32_UPD : VLD3WB<0b1000, "32">;
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// vld3 to double-spaced odd registers.
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def VLD3q8b : VLD3WB<0b0000, "8">;
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def VLD3q16b : VLD3WB<0b0100, "16">;
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def VLD3q32b : VLD3WB<0b1000, "32">;
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def VLD3q8odd_UPD : VLD3WB<0b0000, "8">;
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def VLD3q16odd_UPD : VLD3WB<0b0100, "16">;
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def VLD3q32odd_UPD : VLD3WB<0b1000, "32">;
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// VLD4 : Vector Load (multiple 4-element structures)
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class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -320,14 +320,14 @@ def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
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def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
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// vld4 to double-spaced even registers.
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def VLD4q8a : VLD4WB<0b0000, "8">;
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def VLD4q16a : VLD4WB<0b0100, "16">;
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def VLD4q32a : VLD4WB<0b1000, "32">;
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def VLD4q8_UPD : VLD4WB<0b0000, "8">;
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def VLD4q16_UPD : VLD4WB<0b0100, "16">;
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def VLD4q32_UPD : VLD4WB<0b1000, "32">;
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// vld4 to double-spaced odd registers.
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def VLD4q8b : VLD4WB<0b0000, "8">;
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def VLD4q16b : VLD4WB<0b0100, "16">;
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def VLD4q32b : VLD4WB<0b1000, "32">;
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def VLD4q8odd_UPD : VLD4WB<0b0000, "8">;
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def VLD4q16odd_UPD : VLD4WB<0b0100, "16">;
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def VLD4q32odd_UPD : VLD4WB<0b1000, "32">;
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// VLD1LN : Vector Load (single element to one lane)
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// FIXME: Not yet implemented.
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@ -345,12 +345,12 @@ def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
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def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
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// vld2 to double-spaced even registers.
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def VLD2LNq16a: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32a: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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// vld2 to double-spaced odd registers.
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def VLD2LNq16b: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32b: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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// VLD3LN : Vector Load (single 3-element structure to one lane)
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class VLD3LN<bits<4> op11_8, string Dt>
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@ -366,12 +366,12 @@ def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
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def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
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// vld3 to double-spaced even registers.
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def VLD3LNq16a: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32a: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// vld3 to double-spaced odd registers.
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def VLD3LNq16b: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32b: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// VLD4LN : Vector Load (single 4-element structure to one lane)
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class VLD4LN<bits<4> op11_8, string Dt>
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@ -388,12 +388,12 @@ def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
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def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
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// vld4 to double-spaced even registers.
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def VLD4LNq16a: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32a: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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// vld4 to double-spaced odd registers.
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def VLD4LNq16b: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32b: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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// VLD1DUP : Vector Load (single element to all lanes)
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// VLD2DUP : Vector Load (single 2-element structure to all lanes)
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@ -503,14 +503,14 @@ def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
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"vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
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// vst3 to double-spaced even registers.
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def VST3q8a : VST3WB<0b0000, "8">;
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def VST3q16a : VST3WB<0b0100, "16">;
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def VST3q32a : VST3WB<0b1000, "32">;
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def VST3q8_UPD : VST3WB<0b0000, "8">;
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def VST3q16_UPD : VST3WB<0b0100, "16">;
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def VST3q32_UPD : VST3WB<0b1000, "32">;
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// vst3 to double-spaced odd registers.
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def VST3q8b : VST3WB<0b0000, "8">;
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def VST3q16b : VST3WB<0b0100, "16">;
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def VST3q32b : VST3WB<0b1000, "32">;
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def VST3q8odd_UPD : VST3WB<0b0000, "8">;
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def VST3q16odd_UPD : VST3WB<0b0100, "16">;
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def VST3q32odd_UPD : VST3WB<0b1000, "32">;
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// VST4 : Vector Store (multiple 4-element structures)
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class VST4D<bits<4> op7_4, string Dt>
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@ -534,14 +534,14 @@ def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
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"", []>;
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// vst4 to double-spaced even registers.
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def VST4q8a : VST4WB<0b0000, "8">;
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def VST4q16a : VST4WB<0b0100, "16">;
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def VST4q32a : VST4WB<0b1000, "32">;
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def VST4q8_UPD : VST4WB<0b0000, "8">;
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def VST4q16_UPD : VST4WB<0b0100, "16">;
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def VST4q32_UPD : VST4WB<0b1000, "32">;
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// vst4 to double-spaced odd registers.
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def VST4q8b : VST4WB<0b0000, "8">;
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def VST4q16b : VST4WB<0b0100, "16">;
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def VST4q32b : VST4WB<0b1000, "32">;
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def VST4q8odd_UPD : VST4WB<0b0000, "8">;
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def VST4q16odd_UPD : VST4WB<0b0100, "16">;
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def VST4q32odd_UPD : VST4WB<0b1000, "32">;
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// VST1LN : Vector Store (single element from one lane)
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// FIXME: Not yet implemented.
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@ -559,12 +559,12 @@ def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
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def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
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// vst2 to double-spaced even registers.
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def VST2LNq16a: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32a: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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// vst2 to double-spaced odd registers.
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def VST2LNq16b: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32b: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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// VST3LN : Vector Store (single 3-element structure from one lane)
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class VST3LN<bits<4> op11_8, string Dt>
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@ -579,12 +579,12 @@ def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
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def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
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// vst3 to double-spaced even registers.
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def VST3LNq16a: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VST3LNq32a: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// vst3 to double-spaced odd registers.
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def VST3LNq16b: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VST3LNq32b: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
|
||||
def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
|
||||
|
||||
// VST4LN : Vector Store (single 4-element structure from one lane)
|
||||
class VST4LN<bits<4> op11_8, string Dt>
|
||||
@ -600,12 +600,12 @@ def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
|
||||
def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
|
||||
|
||||
// vst4 to double-spaced even registers.
|
||||
def VST4LNq16a: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
|
||||
def VST4LNq32a: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
|
||||
def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
|
||||
def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
|
||||
|
||||
// vst4 to double-spaced odd registers.
|
||||
def VST4LNq16b: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
|
||||
def VST4LNq32b: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
|
||||
def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
|
||||
def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
|
||||
|
||||
} // mayStore = 1, hasExtraSrcRegAllocReq = 1
|
||||
|
||||
|
||||
@ -64,16 +64,16 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 4;
|
||||
return true;
|
||||
|
||||
case ARM::VLD2LNq16a:
|
||||
case ARM::VLD2LNq32a:
|
||||
case ARM::VLD2LNq16:
|
||||
case ARM::VLD2LNq32:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 2;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD2LNq16b:
|
||||
case ARM::VLD2LNq32b:
|
||||
case ARM::VLD2LNq16odd:
|
||||
case ARM::VLD2LNq32odd:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 2;
|
||||
Offset = 1;
|
||||
@ -91,34 +91,34 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 3;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3q8a:
|
||||
case ARM::VLD3q16a:
|
||||
case ARM::VLD3q32a:
|
||||
case ARM::VLD3q8_UPD:
|
||||
case ARM::VLD3q16_UPD:
|
||||
case ARM::VLD3q32_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3q8b:
|
||||
case ARM::VLD3q16b:
|
||||
case ARM::VLD3q32b:
|
||||
case ARM::VLD3q8odd_UPD:
|
||||
case ARM::VLD3q16odd_UPD:
|
||||
case ARM::VLD3q32odd_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3LNq16a:
|
||||
case ARM::VLD3LNq32a:
|
||||
case ARM::VLD3LNq16:
|
||||
case ARM::VLD3LNq32:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3LNq16b:
|
||||
case ARM::VLD3LNq32b:
|
||||
case ARM::VLD3LNq16odd:
|
||||
case ARM::VLD3LNq32odd:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 1;
|
||||
@ -136,34 +136,34 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 4;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4q8a:
|
||||
case ARM::VLD4q16a:
|
||||
case ARM::VLD4q32a:
|
||||
case ARM::VLD4q8_UPD:
|
||||
case ARM::VLD4q16_UPD:
|
||||
case ARM::VLD4q32_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4q8b:
|
||||
case ARM::VLD4q16b:
|
||||
case ARM::VLD4q32b:
|
||||
case ARM::VLD4q8odd_UPD:
|
||||
case ARM::VLD4q16odd_UPD:
|
||||
case ARM::VLD4q32odd_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4LNq16a:
|
||||
case ARM::VLD4LNq32a:
|
||||
case ARM::VLD4LNq16:
|
||||
case ARM::VLD4LNq32:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4LNq16b:
|
||||
case ARM::VLD4LNq32b:
|
||||
case ARM::VLD4LNq16odd:
|
||||
case ARM::VLD4LNq32odd:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
@ -188,16 +188,16 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 4;
|
||||
return true;
|
||||
|
||||
case ARM::VST2LNq16a:
|
||||
case ARM::VST2LNq32a:
|
||||
case ARM::VST2LNq16:
|
||||
case ARM::VST2LNq32:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 2;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST2LNq16b:
|
||||
case ARM::VST2LNq32b:
|
||||
case ARM::VST2LNq16odd:
|
||||
case ARM::VST2LNq32odd:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 2;
|
||||
Offset = 1;
|
||||
@ -215,34 +215,34 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 3;
|
||||
return true;
|
||||
|
||||
case ARM::VST3q8a:
|
||||
case ARM::VST3q16a:
|
||||
case ARM::VST3q32a:
|
||||
case ARM::VST3q8_UPD:
|
||||
case ARM::VST3q16_UPD:
|
||||
case ARM::VST3q32_UPD:
|
||||
FirstOpnd = 5;
|
||||
NumRegs = 3;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST3q8b:
|
||||
case ARM::VST3q16b:
|
||||
case ARM::VST3q32b:
|
||||
case ARM::VST3q8odd_UPD:
|
||||
case ARM::VST3q16odd_UPD:
|
||||
case ARM::VST3q32odd_UPD:
|
||||
FirstOpnd = 5;
|
||||
NumRegs = 3;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST3LNq16a:
|
||||
case ARM::VST3LNq32a:
|
||||
case ARM::VST3LNq16:
|
||||
case ARM::VST3LNq32:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 3;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST3LNq16b:
|
||||
case ARM::VST3LNq32b:
|
||||
case ARM::VST3LNq16odd:
|
||||
case ARM::VST3LNq32odd:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 3;
|
||||
Offset = 1;
|
||||
@ -260,34 +260,34 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 4;
|
||||
return true;
|
||||
|
||||
case ARM::VST4q8a:
|
||||
case ARM::VST4q16a:
|
||||
case ARM::VST4q32a:
|
||||
case ARM::VST4q8_UPD:
|
||||
case ARM::VST4q16_UPD:
|
||||
case ARM::VST4q32_UPD:
|
||||
FirstOpnd = 5;
|
||||
NumRegs = 4;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST4q8b:
|
||||
case ARM::VST4q16b:
|
||||
case ARM::VST4q32b:
|
||||
case ARM::VST4q8odd_UPD:
|
||||
case ARM::VST4q16odd_UPD:
|
||||
case ARM::VST4q32odd_UPD:
|
||||
FirstOpnd = 5;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST4LNq16a:
|
||||
case ARM::VST4LNq32a:
|
||||
case ARM::VST4LNq16:
|
||||
case ARM::VST4LNq32:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 4;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST4LNq16b:
|
||||
case ARM::VST4LNq32b:
|
||||
case ARM::VST4LNq16odd:
|
||||
case ARM::VST4LNq32odd:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user