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https://github.com/c64scene-ar/llvm-6502.git
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- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1296,9 +1296,23 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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MachineOperand &O = ri.getOperand();
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++ri;
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if (MI->isDebugValue()) {
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// Remove debug info for now.
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O.setReg(0U);
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DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
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// Modify DBG_VALUE now that the value is in a spill slot.
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uint64_t Offset = MI->getOperand(1).getImm();
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const MDNode *MDPtr = MI->getOperand(2).getMetadata();
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DebugLoc DL = MI->getDebugLoc();
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MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot, Offset,
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MDPtr, DL);
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if (NewDV) {
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DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
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ReplaceMachineInstrInMaps(MI, NewDV);
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MachineBasicBlock *MBB = MI->getParent();
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MBB->insert(MBB->erase(MI), NewDV);
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} else {
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DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
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RemoveMachineInstrFromMaps(MI);
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vrm.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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}
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continue;
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}
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assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
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@ -507,7 +507,6 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
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/// EmitDbgValue - Generate machine instruction for a dbg_value node.
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///
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MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
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MachineBasicBlock *InsertBB,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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uint64_t Offset = SD->getOffset();
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@ -518,8 +517,7 @@ MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
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// Stack address; this needs to be lowered in target-dependent fashion.
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// EmitTargetCodeForFrameDebugValue is responsible for allocation.
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unsigned FrameIx = SD->getFrameIx();
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TLI->EmitTargetCodeForFrameDebugValue(InsertBB, FrameIx, Offset, MDPtr, DL);
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return 0;
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return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
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}
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// Otherwise, we're going to create an instruction here.
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const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
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@ -103,7 +103,6 @@ public:
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/// EmitDbgValue - Generate machine instruction for a dbg_value node.
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///
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MachineInstr *EmitDbgValue(SDDbgValue *SD,
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MachineBasicBlock *InsertBB,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
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@ -449,9 +449,11 @@ static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
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continue;
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unsigned DVOrder = DVs[i]->getOrder();
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if (DVOrder == ++Order) {
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MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
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Orders.push_back(std::make_pair(DVOrder, DbgMI));
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BB->insert(InsertPos, DbgMI);
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MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap, EM);
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if (DbgMI) {
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Orders.push_back(std::make_pair(DVOrder, DbgMI));
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BB->insert(InsertPos, DbgMI);
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}
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DVs[i]->setIsInvalidated();
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}
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}
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@ -540,13 +542,15 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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#endif
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if ((*DI)->isInvalidated())
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continue;
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MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
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if (!LastOrder)
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// Insert to start of the BB (after PHIs).
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BB->insert(BBBegin, DbgMI);
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else {
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MachineBasicBlock::iterator Pos = MI;
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MIBB->insert(llvm::next(Pos), DbgMI);
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MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
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if (DbgMI) {
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if (!LastOrder)
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// Insert to start of the BB (after PHIs).
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BB->insert(BBBegin, DbgMI);
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else {
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MachineBasicBlock::iterator Pos = MI;
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MIBB->insert(llvm::next(Pos), DbgMI);
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}
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}
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}
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LastOrder = Order;
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@ -558,8 +562,9 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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MachineBasicBlock *InsertBB = Emitter.getBlock();
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MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
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if (!(*DI)->isInvalidated()) {
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MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
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InsertBB->insert(Pos, DbgMI);
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MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
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if (DbgMI)
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InsertBB->insert(Pos, DbgMI);
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}
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++DI;
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}
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