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https://github.com/c64scene-ar/llvm-6502.git
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[InstCombine][x86] Constant fold psll intrinsics.
This excludes avx512 as I don't have hardware to verify. It excludes _dq
variants because they are represented in the IR as <{2,4} x i64> when it's
actually a byte shift of the entire i{128,265}.
This also excludes _dq_bs as they aren't at all supported by the backend.
There are also no corresponding instructions in the ISA. I have no idea why
they exist...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207058 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael J. Spencer
parent
b53610141c
commit
96363d5001
@ -556,6 +556,47 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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// Constant fold <A x Bi> << Ci.
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// FIXME: We don't handle _dq because it's a shift of an i128, but is
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// represented in the IR as <2 x i64>. A per element shift is wrong.
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_sse2_pslli_d:
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case Intrinsic::x86_sse2_pslli_q:
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case Intrinsic::x86_sse2_pslli_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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case Intrinsic::x86_avx2_psll_w:
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case Intrinsic::x86_avx2_pslli_d:
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case Intrinsic::x86_avx2_pslli_q:
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case Intrinsic::x86_avx2_pslli_w: {
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// Simplify if count is constant. To 0 if > BitWidth, otherwise to shl.
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auto CDV = dyn_cast<ConstantDataVector>(II->getArgOperand(1));
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auto CInt = dyn_cast<ConstantInt>(II->getArgOperand(1));
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if (!CDV && !CInt)
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break;
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ConstantInt *Count;
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if (CDV)
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Count = cast<ConstantInt>(CDV->getElementAsConstant(0));
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else
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Count = CInt;
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auto Vec = II->getArgOperand(0);
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auto VT = cast<VectorType>(Vec->getType());
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if (Count->getZExtValue() >
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VT->getElementType()->getPrimitiveSizeInBits() - 1)
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return ReplaceInstUsesWith(
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CI, ConstantAggregateZero::get(Vec->getType()));
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else {
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unsigned VWidth = VT->getNumElements();
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// Get a constant vector of the same type as the first operand.
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auto VTCI = ConstantInt::get(VT->getElementType(), Count->getZExtValue());
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return BinaryOperator::CreateShl(
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Vec, Builder->CreateVectorSplat(VWidth, VTCI));
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}
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break;
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}
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case Intrinsic::x86_sse41_pmovsxbw:
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case Intrinsic::x86_sse41_pmovsxwd:
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@ -1,4 +1,5 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i16 @test1(float %f) {
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entry:
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@ -337,3 +338,112 @@ define <4 x double> @test_vpermilvar_pd_256(<4 x double> %v) {
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%a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
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ret <4 x double> %a
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}
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define <2 x i64> @test_sse2_1() nounwind readnone uwtable {
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%S = bitcast i32 1 to i32
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%1 = zext i32 %S to i64
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%2 = insertelement <2 x i64> undef, i64 %1, i32 0
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%3 = insertelement <2 x i64> %2, i64 0, i32 1
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%4 = bitcast <2 x i64> %3 to <8 x i16>
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%5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4)
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%6 = bitcast <8 x i16> %5 to <4 x i32>
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%7 = bitcast <2 x i64> %3 to <4 x i32>
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%8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7)
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%9 = bitcast <4 x i32> %8 to <2 x i64>
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%10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3)
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%11 = bitcast <2 x i64> %10 to <8 x i16>
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%12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S)
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%13 = bitcast <8 x i16> %12 to <4 x i32>
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%14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S)
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%15 = bitcast <4 x i32> %14 to <2 x i64>
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%16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S)
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ret <2 x i64> %16
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; CHECK: test_sse2_1
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; CHECK: ret <2 x i64> <i64 72058418680037440, i64 144117112246370624>
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}
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define <4 x i64> @test_avx2_1() nounwind readnone uwtable {
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%S = bitcast i32 1 to i32
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%1 = zext i32 %S to i64
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%2 = insertelement <2 x i64> undef, i64 %1, i32 0
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%3 = insertelement <2 x i64> %2, i64 0, i32 1
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%4 = bitcast <2 x i64> %3 to <8 x i16>
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%5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4)
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%6 = bitcast <16 x i16> %5 to <8 x i32>
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%7 = bitcast <2 x i64> %3 to <4 x i32>
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%8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7)
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%9 = bitcast <8 x i32> %8 to <4 x i64>
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%10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3)
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%11 = bitcast <4 x i64> %10 to <16 x i16>
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%12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S)
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%13 = bitcast <16 x i16> %12 to <8 x i32>
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%14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S)
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%15 = bitcast <8 x i32> %14 to <4 x i64>
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%16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S)
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ret <4 x i64> %16
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; CHECK: test_avx2_1
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; CHECK: ret <4 x i64> <i64 64, i64 128, i64 192, i64 256>
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}
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define <2 x i64> @test_sse2_0() nounwind readnone uwtable {
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%S = bitcast i32 128 to i32
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%1 = zext i32 %S to i64
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%2 = insertelement <2 x i64> undef, i64 %1, i32 0
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%3 = insertelement <2 x i64> %2, i64 0, i32 1
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%4 = bitcast <2 x i64> %3 to <8 x i16>
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%5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4)
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%6 = bitcast <8 x i16> %5 to <4 x i32>
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%7 = bitcast <2 x i64> %3 to <4 x i32>
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%8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7)
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%9 = bitcast <4 x i32> %8 to <2 x i64>
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%10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3)
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%11 = bitcast <2 x i64> %10 to <8 x i16>
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%12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S)
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%13 = bitcast <8 x i16> %12 to <4 x i32>
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%14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S)
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%15 = bitcast <4 x i32> %14 to <2 x i64>
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%16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S)
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ret <2 x i64> %16
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; CHECK: test_sse2_0
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; CHECK: ret <2 x i64> zeroinitializer
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}
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define <4 x i64> @test_avx2_0() nounwind readnone uwtable {
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%S = bitcast i32 128 to i32
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%1 = zext i32 %S to i64
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%2 = insertelement <2 x i64> undef, i64 %1, i32 0
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%3 = insertelement <2 x i64> %2, i64 0, i32 1
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%4 = bitcast <2 x i64> %3 to <8 x i16>
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%5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4)
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%6 = bitcast <16 x i16> %5 to <8 x i32>
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%7 = bitcast <2 x i64> %3 to <4 x i32>
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%8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7)
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%9 = bitcast <8 x i32> %8 to <4 x i64>
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%10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3)
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%11 = bitcast <4 x i64> %10 to <16 x i16>
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%12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S)
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%13 = bitcast <16 x i16> %12 to <8 x i32>
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%14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S)
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%15 = bitcast <8 x i32> %14 to <4 x i64>
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%16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S)
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ret <4 x i64> %16
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; CHECK: test_avx2_0
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; CHECK: ret <4 x i64> zeroinitializer
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}
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declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) #1
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declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) #1
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declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) #1
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declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) #1
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declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) #1
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declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) #1
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declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) #1
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) #1
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) #1
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declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) #1
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declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) #1
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declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) #1
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attributes #1 = { nounwind readnone }
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