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convert test to use the existing classes that the multipatterns
use. Since TEST is completely different than all other binops, don't define a multipattern for it. This completes factorization of binops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -600,8 +600,8 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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// BinOpRR - Instructions like "add reg, reg, reg".
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class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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dag outlist, list<dag> pattern>
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: ITy<opcode, MRMDestReg, typeinfo, outlist,
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dag outlist, list<dag> pattern, Format f = MRMDestReg>
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: ITy<opcode, f, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
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@ -616,10 +616,11 @@ class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
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// just a EFLAGS as a result.
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class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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SDPatternOperator opnode, Format f = MRMDestReg>
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: BinOpRR<opcode, mnemonic, typeinfo, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
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f>;
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// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
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// both a regclass and EFLAGS as a result.
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@ -655,7 +656,7 @@ class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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// BinOpRM_F - Instructions like "cmp reg, [mem]".
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class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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SDPatternOperator opnode>
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: BinOpRM<opcode, mnemonic, typeinfo, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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@ -685,7 +686,7 @@ class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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// BinOpRI_F - Instructions like "cmp reg, imm".
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class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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SDPatternOperator opnode, Format f>
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: BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
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@ -749,8 +750,8 @@ class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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// BinOpMI - Instructions like "add [mem], imm".
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class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
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Format f, list<dag> pattern>
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: ITy<0x80, f, typeinfo,
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Format f, list<dag> pattern, bits<8> opcode = 0x80>
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: ITy<opcode, f, typeinfo,
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(outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
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mnemonic, "{$src, $dst|$dst, $src}", pattern> {
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let ImmT = typeinfo.ImmEncoding;
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@ -766,10 +767,11 @@ class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
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// BinOpMI_F - Instructions like "cmp [mem], imm".
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class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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SDPatternOperator opnode, Format f, bits<8> opcode = 0x80>
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: BinOpMI<mnemonic, typeinfo, f,
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[(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
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typeinfo.ImmOperator:$src))]>;
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typeinfo.ImmOperator:$src))],
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opcode>;
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// BinOpMI8 - Instructions like "add [mem], imm8".
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class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
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@ -1008,98 +1010,45 @@ let Uses = [EFLAGS] in {
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defm SBB : ArithBinOp_R<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, sube, 0, 0>;
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}
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//===----------------------------------------------------------------------===//
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// Test instructions are just like AND, except they don't generate a result.
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//
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let Defs = [EFLAGS] in {
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let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
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def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
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"test{b}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
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def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
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"test{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
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0))]>,
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OpSize;
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def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
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"test{l}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
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0))]>;
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def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
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"test{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
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}
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def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
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"test{b}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
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0))]>;
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def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
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"test{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR16:$src1,
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(loadi16 addr:$src2)), 0))]>, OpSize;
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def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
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"test{l}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR32:$src1,
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(loadi32 addr:$src2)), 0))]>;
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def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
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"test{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
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0))]>;
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def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
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(outs), (ins GR8:$src1, i8imm:$src2),
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"test{b}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
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def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
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(outs), (ins GR16:$src1, i16imm:$src2),
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"test{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
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OpSize;
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def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
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(outs), (ins GR32:$src1, i32imm:$src2),
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"test{l}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
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def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
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(ins GR64:$src1, i64i32imm:$src2),
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"test{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
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0))]>;
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def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
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(outs), (ins i8mem:$src1, i8imm:$src2),
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"test{b}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
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0))]>;
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def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
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(outs), (ins i16mem:$src1, i16imm:$src2),
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"test{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
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0))]>, OpSize;
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def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
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(outs), (ins i32mem:$src1, i32imm:$src2),
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"test{l}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
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0))]>;
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def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
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(ins i64mem:$src1, i64i32imm:$src2),
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"test{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
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i64immSExt32:$src2), 0))]>;
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def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
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"test{b}\t{$src, %al|%al, $src}", []>;
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def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
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"test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
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"test{l}\t{$src, %eax|%eax, $src}", []>;
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def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
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"test{q}\t{$src, %rax|%rax, $src}", []>;
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} // Defs = [EFLAGS]
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//===----------------------------------------------------------------------===//
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// Integer comparisons
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defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
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//===----------------------------------------------------------------------===//
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// Semantically, test instructions are similar like AND, except they don't
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// generate a result. From an encoding perspective, they are very different:
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// they don't have all the usual imm8 and REV forms, and are encoded into a
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// different space.
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def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
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(X86cmp (and_su node:$lhs, node:$rhs), 0)>;
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let Defs = [EFLAGS] in {
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let isCommutable = 1 in {
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def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
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def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
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def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
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def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
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} // isCommutable
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def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
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def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
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def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
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def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
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def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
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def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
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def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
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def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
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def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
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def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
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def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
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def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
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def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL>;
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def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX>;
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def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX>;
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def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX>;
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}
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