diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h
index 5fdcac5cf68..1df8c5e3b5d 100644
--- a/include/llvm/ADT/Triple.h
+++ b/include/llvm/ADT/Triple.h
@@ -67,9 +67,7 @@ public:
     sparc,      // Sparc: sparc
     sparcv9,    // Sparcv9: Sparcv9
     sparcel,    // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
-    mos6502,    // Mos6502: mos6502
-    mos6502v9,  // Mos6502v9: Sparcv9
-    mos6502el,  // Mos6502: (endianness = little). NB: 'Mos6502le' is a CPU variant
+    mos6502,    // MOS 6502: mos6502
     systemz,    // SystemZ: s390x
     tce,        // TCE (http://tce.cs.tut.fi/): tce
     thumb,      // Thumb (little endian): thumb, thumbv.*
diff --git a/lib/MC/MCObjectFileInfo.cpp b/lib/MC/MCObjectFileInfo.cpp
index bf924f105b5..3cf54737774 100644
--- a/lib/MC/MCObjectFileInfo.cpp
+++ b/lib/MC/MCObjectFileInfo.cpp
@@ -348,7 +348,6 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(Triple T) {
     break;
   case Triple::sparcel:
   case Triple::sparc:
-  case Triple::mos6502el:
   case Triple::mos6502:
     if (RelocM == Reloc::PIC_) {
       LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
@@ -363,7 +362,6 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(Triple T) {
     }
     break;
   case Triple::sparcv9:
-  case Triple::mos6502v9:
     LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
     if (RelocM == Reloc::PIC_) {
       PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp
index adac3edb9f5..1dfe3755eea 100644
--- a/lib/Support/Triple.cpp
+++ b/lib/Support/Triple.cpp
@@ -42,8 +42,6 @@ const char *Triple::getArchTypeName(ArchType Kind) {
   case sparcv9:     return "sparcv9";
   case sparcel:     return "sparcel";
   case mos6502:     return "mos6502";
-  case mos6502v9:   return "mos6502v9";
-  case mos6502el:   return "mos6502el";
   case systemz:     return "s390x";
   case tce:         return "tce";
   case thumb:       return "thumb";
@@ -104,9 +102,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
   case sparcel:
   case sparc:       return "sparc";
 
-  case mos6502v9:
-  case mos6502el:
-  case mos6502:       return "mos6502";
+  case mos6502:     return "mos6502";
 
   case systemz:     return "s390";
 
@@ -249,8 +245,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
     .Case("sparcel", sparcel)
     .Case("sparcv9", sparcv9)
     .Case("mos6502", mos6502)
-    .Case("mos6502el", mos6502el)
-    .Case("mos6502v9", mos6502v9)
     .Case("systemz", systemz)
     .Case("tce", tce)
     .Case("thumb", thumb)
@@ -364,8 +358,6 @@ static Triple::ArchType parseArch(StringRef ArchName) {
     .Case("sparcel", Triple::sparcel)
     .Cases("sparcv9", "sparc64", Triple::sparcv9)
     .Case("mos6502", Triple::mos6502)
-    .Case("mos6502el", Triple::mos6502el)
-    .Cases("mos6502v9", "mos650264", Triple::mos6502v9)
     .Case("tce", Triple::tce)
     .Case("xcore", Triple::xcore)
     .Case("nvptx", Triple::nvptx)
@@ -540,8 +532,6 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::amdgcn:
   case Triple::sparc:
   case Triple::sparcv9:
-  case Triple::mos6502:
-  case Triple::mos6502v9:
   case Triple::systemz:
   case Triple::xcore:
   case Triple::ppc64le:
@@ -1025,7 +1015,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
   case llvm::Triple::mos6502:
-  case llvm::Triple::mos6502el:
   case llvm::Triple::tce:
   case llvm::Triple::thumb:
   case llvm::Triple::thumbeb:
@@ -1051,7 +1040,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::sparcv9:
-  case llvm::Triple::mos6502v9:
   case llvm::Triple::systemz:
   case llvm::Triple::x86_64:
   case llvm::Triple::amdil64:
@@ -1106,7 +1094,6 @@ Triple Triple::get32BitArchVariant() const {
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::mos6502:
-  case Triple::mos6502el:
   case Triple::tce:
   case Triple::thumb:
   case Triple::thumbeb:
@@ -1123,7 +1110,6 @@ Triple Triple::get32BitArchVariant() const {
   case Triple::nvptx64:   T.setArch(Triple::nvptx);   break;
   case Triple::ppc64:     T.setArch(Triple::ppc);     break;
   case Triple::sparcv9:   T.setArch(Triple::sparc);   break;
-  case Triple::mos6502v9: T.setArch(Triple::mos6502); break;
   case Triple::x86_64:    T.setArch(Triple::x86);     break;
   case Triple::amdil64:   T.setArch(Triple::amdil);   break;
   case Triple::hsail64:   T.setArch(Triple::hsail);   break;
@@ -1148,7 +1134,7 @@ Triple Triple::get64BitArchVariant() const {
   case Triple::thumbeb:
   case Triple::xcore:
   case Triple::sparcel:
-  case Triple::mos6502el:
+  case Triple::mos6502:
   case Triple::shave:
     T.setArch(UnknownArch);
     break;
@@ -1168,7 +1154,6 @@ Triple Triple::get64BitArchVariant() const {
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::sparcv9:
-  case Triple::mos6502v9:
   case Triple::systemz:
   case Triple::x86_64:
   case Triple::wasm64:
@@ -1181,7 +1166,6 @@ Triple Triple::get64BitArchVariant() const {
   case Triple::nvptx:   T.setArch(Triple::nvptx64);   break;
   case Triple::ppc:     T.setArch(Triple::ppc64);     break;
   case Triple::sparc:   T.setArch(Triple::sparcv9);   break;
-  case Triple::mos6502: T.setArch(Triple::mos6502v9); break;
   case Triple::x86:     T.setArch(Triple::x86_64);    break;
   case Triple::amdil:   T.setArch(Triple::amdil64);   break;
   case Triple::hsail:   T.setArch(Triple::hsail64);   break;
@@ -1233,8 +1217,6 @@ Triple Triple::getBigEndianArchVariant() const {
   case Triple::ppc:
   case Triple::sparc:
   case Triple::sparcv9:
-  case Triple::mos6502:
-  case Triple::mos6502v9:
   case Triple::systemz:
   case Triple::tce:
   case Triple::thumbeb:
@@ -1247,7 +1229,6 @@ Triple Triple::getBigEndianArchVariant() const {
   case Triple::mipsel:  T.setArch(Triple::mips);       break;
   case Triple::ppc64le: T.setArch(Triple::ppc64);      break;
   case Triple::sparcel: T.setArch(Triple::sparc);      break;
-  case Triple::mos6502el: T.setArch(Triple::mos6502);  break;
   }
   return T;
 }
@@ -1258,7 +1239,6 @@ Triple Triple::getLittleEndianArchVariant() const {
   case Triple::UnknownArch:
   case Triple::ppc:
   case Triple::sparcv9:
-  case Triple::mos6502v9:
   case Triple::systemz:
   case Triple::tce:
 
@@ -1290,7 +1270,7 @@ Triple Triple::getLittleEndianArchVariant() const {
   case Triple::r600:
   case Triple::shave:
   case Triple::sparcel:
-  case Triple::mos6502el:
+  case Triple::mos6502:
   case Triple::spir64:
   case Triple::spir:
   case Triple::thumb:
@@ -1308,7 +1288,6 @@ Triple Triple::getLittleEndianArchVariant() const {
   case Triple::mips:       T.setArch(Triple::mipsel);   break;
   case Triple::ppc64:      T.setArch(Triple::ppc64le);  break;
   case Triple::sparc:      T.setArch(Triple::sparcel);  break;
-  case Triple::mos6502:    T.setArch(Triple::mos6502el);  break;
   }
   return T;
 }
diff --git a/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp b/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp
index b2c91d54ad6..21d53c7e689 100644
--- a/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp
+++ b/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp
@@ -77,7 +77,7 @@ class Mos6502AsmParser : public MCTargetAsmParser {
   bool parseDirectiveWord(unsigned Size, SMLoc L);
 
   bool is64Bit() const {
-    return STI.getTargetTriple().getArchName().startswith("mos6502v9");
+    return false;
   }
 
   void expandSET(MCInst &Inst, SMLoc IDLoc,
@@ -1026,9 +1026,7 @@ bool Mos6502AsmParser::matchMos6502AsmModifiers(const MCExpr *&EVal,
 }
 
 extern "C" void LLVMInitializeMos6502AsmParser() {
-  RegisterMCAsmParser<Mos6502AsmParser> A(TheMos6502Target);
-  RegisterMCAsmParser<Mos6502AsmParser> B(TheMos6502V9Target);
-  RegisterMCAsmParser<Mos6502AsmParser> C(TheMos6502elTarget);
+  RegisterMCAsmParser<Mos6502AsmParser> C(TheMos6502Target);
 }
 
 #define GET_REGISTER_MATCHER
diff --git a/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp b/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp
index 9e3375b54a5..94cd6f1d7ad 100644
--- a/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp
+++ b/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp
@@ -44,7 +44,7 @@ public:
 }
 
 namespace llvm {
-extern Target TheMos6502Target, TheMos6502V9Target, TheMos6502elTarget;
+extern Target TheMos6502Target;
 }
 
 static MCDisassembler *createMos6502Disassembler(const Target &T,
@@ -58,10 +58,6 @@ extern "C" void LLVMInitializeMos6502Disassembler() {
   // Register the disassembler.
   TargetRegistry::RegisterMCDisassembler(TheMos6502Target,
                                          createMos6502Disassembler);
-  TargetRegistry::RegisterMCDisassembler(TheMos6502V9Target,
-                                         createMos6502Disassembler);
-  TargetRegistry::RegisterMCDisassembler(TheMos6502elTarget,
-                                         createMos6502Disassembler);
 }
 
 static const unsigned IntRegDecoderTable[] = {
diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502AsmBackend.cpp b/lib/Target/Mos6502/MCTargetDesc/Mos6502AsmBackend.cpp
index 07d909c0834..fa48cfc55e1 100644
--- a/lib/Target/Mos6502/MCTargetDesc/Mos6502AsmBackend.cpp
+++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502AsmBackend.cpp
@@ -106,8 +106,8 @@ namespace {
   public:
     Mos6502AsmBackend(const Target &T)
         : MCAsmBackend(), TheTarget(T),
-          IsLittleEndian(StringRef(TheTarget.getName()) == "mos6502el"),
-          Is64Bit(StringRef(TheTarget.getName()) == "mos6502v9") {}
+          IsLittleEndian(true),
+          Is64Bit(false) {}
 
     unsigned getNumFixupKinds() const override {
       return Mos6502::NumTargetFixupKinds;
diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCAsmInfo.cpp b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCAsmInfo.cpp
index 60746ed9a92..61d174f797e 100644
--- a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCAsmInfo.cpp
+++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCAsmInfo.cpp
@@ -21,8 +21,8 @@ using namespace llvm;
 void Mos6502ELFMCAsmInfo::anchor() {}
 
 Mos6502ELFMCAsmInfo::Mos6502ELFMCAsmInfo(const Triple &TheTriple) {
-  bool isV9 = (TheTriple.getArch() == Triple::mos6502v9);
-  IsLittleEndian = (TheTriple.getArch() == Triple::mos6502el);
+  bool isV9 = false;
+  IsLittleEndian = true;
 
   if (isV9) {
     PointerSize = CalleeSaveStackSlotSize = 8;
diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp
index 846112bb55b..57fbf9ffd73 100644
--- a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp
+++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp
@@ -42,15 +42,6 @@ static MCAsmInfo *createMos6502MCAsmInfo(const MCRegisterInfo &MRI,
   return MAI;
 }
 
-static MCAsmInfo *createMos6502V9MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new Mos6502ELFMCAsmInfo(TT);
-  unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
-  MAI->addInitialFrameState(Inst);
-  return MAI;
-}
-
 static MCInstrInfo *createMos6502MCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitMos6502MCInstrInfo(X);
@@ -66,7 +57,7 @@ static MCRegisterInfo *createMos6502MCRegisterInfo(const Triple &TT) {
 static MCSubtargetInfo *
 createMos6502MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
-    CPU = (TT.getArch() == Triple::mos6502v9) ? "v9" : "v8";
+    CPU = "v8";
   return createMos6502MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
@@ -99,28 +90,6 @@ static MCCodeGenInfo *createMos6502MCCodeGenInfo(const Triple &TT,
   return X;
 }
 
-static MCCodeGenInfo *createMos6502V9MCCodeGenInfo(const Triple &TT,
-                                                 Reloc::Model RM,
-                                                 CodeModel::Model CM,
-                                                 CodeGenOpt::Level OL) {
-  MCCodeGenInfo *X = new MCCodeGenInfo();
-
-  // The default 64-bit code model is abs44/pic32 and the default 64-bit
-  // code model for JIT is abs64.
-  switch (CM) {
-  default:  break;
-  case CodeModel::Default:
-    CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
-    break;
-  case CodeModel::JITDefault:
-    CM = CodeModel::Large;
-    break;
-  }
-
-  X->initMCCodeGenInfo(RM, CM, OL);
-  return X;
-}
-
 static MCTargetStreamer *
 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
   return new Mos6502TargetELFStreamer(S);
@@ -143,11 +112,9 @@ static MCInstPrinter *createMos6502MCInstPrinter(const Triple &T,
 
 extern "C" void LLVMInitializeMos6502TargetMC() {
   // Register the MC asm info.
-  RegisterMCAsmInfoFn X(TheMos6502Target, createMos6502MCAsmInfo);
-  RegisterMCAsmInfoFn Y(TheMos6502V9Target, createMos6502V9MCAsmInfo);
-  RegisterMCAsmInfoFn Z(TheMos6502elTarget, createMos6502MCAsmInfo);
+  RegisterMCAsmInfoFn Z(TheMos6502Target, createMos6502MCAsmInfo);
 
-  for (Target *T : {&TheMos6502Target, &TheMos6502V9Target, &TheMos6502elTarget}) {
+  for (Target *T : {&TheMos6502Target}) {
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createMos6502MCInstrInfo);
 
@@ -177,8 +144,4 @@ extern "C" void LLVMInitializeMos6502TargetMC() {
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheMos6502Target,
                                         createMos6502MCCodeGenInfo);
-  TargetRegistry::RegisterMCCodeGenInfo(TheMos6502V9Target,
-                                        createMos6502V9MCCodeGenInfo);
-  TargetRegistry::RegisterMCCodeGenInfo(TheMos6502elTarget,
-                                        createMos6502MCCodeGenInfo);
 }
diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.h b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.h
index 191dd7b8bf0..55888003443 100644
--- a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.h
+++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.h
@@ -31,8 +31,6 @@ class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheMos6502Target;
-extern Target TheMos6502V9Target;
-extern Target TheMos6502elTarget;
 
 MCCodeEmitter *createMos6502MCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
diff --git a/lib/Target/Mos6502/Mos6502AsmPrinter.cpp b/lib/Target/Mos6502/Mos6502AsmPrinter.cpp
index d483917628c..cd78041e6c5 100644
--- a/lib/Target/Mos6502/Mos6502AsmPrinter.cpp
+++ b/lib/Target/Mos6502/Mos6502AsmPrinter.cpp
@@ -32,6 +32,7 @@
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
+
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
@@ -443,7 +444,5 @@ bool Mos6502AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 
 // Force static initialization.
 extern "C" void LLVMInitializeMos6502AsmPrinter() {
-  RegisterAsmPrinter<Mos6502AsmPrinter> X(TheMos6502Target);
-  RegisterAsmPrinter<Mos6502AsmPrinter> Y(TheMos6502V9Target);
-  RegisterAsmPrinter<Mos6502AsmPrinter> Z(TheMos6502elTarget);
+  RegisterAsmPrinter<Mos6502AsmPrinter> Z(TheMos6502Target);
 }
diff --git a/lib/Target/Mos6502/Mos6502TargetMachine.cpp b/lib/Target/Mos6502/Mos6502TargetMachine.cpp
index ec68f5f7823..8990ce474e6 100644
--- a/lib/Target/Mos6502/Mos6502TargetMachine.cpp
+++ b/lib/Target/Mos6502/Mos6502TargetMachine.cpp
@@ -16,38 +16,27 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/TargetRegistry.h"
+
 using namespace llvm;
 
 extern "C" void LLVMInitializeMos6502Target() {
   // Register the target.
-  RegisterTargetMachine<Mos6502V8TargetMachine> X(TheMos6502Target);
-  RegisterTargetMachine<Mos6502V9TargetMachine> Y(TheMos6502V9Target);
-  RegisterTargetMachine<Mos6502elTargetMachine> Z(TheMos6502elTarget);
+  RegisterTargetMachine<Mos6502TargetMachine> Z(TheMos6502Target);
 }
 
-static std::string computeDataLayout(const Triple &T, bool is64Bit) {
-  // Mos6502 is typically big endian, but some are little.
-  std::string Ret = T.getArch() == Triple::mos6502el ? "e" : "E";
+static std::string computeDataLayout(const Triple &T) {
+  std::string Ret = "e";
   Ret += "-m:e";
-
-  // Some ABIs have 32bit pointers.
-  if (!is64Bit)
-    Ret += "-p:32:32";
+  Ret += "-p:32:32";
 
   // Alignments for 64 bit integers.
   Ret += "-i64:64";
 
   // On Mos6502V9 128 floats are aligned to 128 bits, on others only to 64.
   // On Mos6502V9 registers can hold 64 or 32 bits, on others only 32.
-  if (is64Bit)
-    Ret += "-n32:64";
-  else
-    Ret += "-f128:64-n32";
+  Ret += "-f128:64-n32";
 
-  if (is64Bit)
-    Ret += "-S128";
-  else
-    Ret += "-S64";
+  Ret += "-S64";
 
   return Ret;
 }
@@ -58,11 +47,11 @@ Mos6502TargetMachine::Mos6502TargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL, bool is64bit)
-    : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
+                                       CodeGenOpt::Level OL)
+    : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         RM, CM, OL),
       TLOF(make_unique<Mos6502ELFTargetObjectFile>()),
-      Subtarget(TT, CPU, FS, *this, is64bit) {
+      Subtarget(TT, CPU, FS, *this, false) {
   initAsmInfo();
 }
 
@@ -103,30 +92,3 @@ bool Mos6502PassConfig::addInstSelector() {
 void Mos6502PassConfig::addPreEmitPass(){
   addPass(createMos6502DelaySlotFillerPass(getMos6502TargetMachine()));
 }
-
-void Mos6502V8TargetMachine::anchor() { }
-
-Mos6502V8TargetMachine::Mos6502V8TargetMachine(const Target &T, const Triple &TT,
-                                           StringRef CPU, StringRef FS,
-                                           const TargetOptions &Options,
-                                           Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : Mos6502TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
-
-void Mos6502V9TargetMachine::anchor() { }
-
-Mos6502V9TargetMachine::Mos6502V9TargetMachine(const Target &T, const Triple &TT,
-                                           StringRef CPU, StringRef FS,
-                                           const TargetOptions &Options,
-                                           Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : Mos6502TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
-
-void Mos6502elTargetMachine::anchor() {}
-
-Mos6502elTargetMachine::Mos6502elTargetMachine(const Target &T, const Triple &TT,
-                                           StringRef CPU, StringRef FS,
-                                           const TargetOptions &Options,
-                                           Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : Mos6502TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
diff --git a/lib/Target/Mos6502/Mos6502TargetMachine.h b/lib/Target/Mos6502/Mos6502TargetMachine.h
index 9b0d824946c..2f356b52223 100644
--- a/lib/Target/Mos6502/Mos6502TargetMachine.h
+++ b/lib/Target/Mos6502/Mos6502TargetMachine.h
@@ -23,11 +23,11 @@ namespace llvm {
 class Mos6502TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   Mos6502Subtarget Subtarget;
+
 public:
   Mos6502TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
-                     Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
-                     bool is64bit);
+                     Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL);
   ~Mos6502TargetMachine() override;
 
   const Mos6502Subtarget *getSubtargetImpl(const Function &) const override {
@@ -41,38 +41,6 @@ public:
   }
 };
 
-/// Mos6502V8TargetMachine - Mos6502 32-bit target machine
-///
-class Mos6502V8TargetMachine : public Mos6502TargetMachine {
-  virtual void anchor();
-public:
-  Mos6502V8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
-                       StringRef FS, const TargetOptions &Options,
-                       Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
-};
-
-/// Mos6502V9TargetMachine - Mos6502 64-bit target machine
-///
-class Mos6502V9TargetMachine : public Mos6502TargetMachine {
-  virtual void anchor();
-public:
-  Mos6502V9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
-                       StringRef FS, const TargetOptions &Options,
-                       Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
-};
-
-class Mos6502elTargetMachine : public Mos6502TargetMachine {
-  virtual void anchor();
-
-public:
-  Mos6502elTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
-                       StringRef FS, const TargetOptions &Options,
-                       Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
-};
-
 } // end namespace llvm
 
 #endif
diff --git a/lib/Target/Mos6502/TargetInfo/Mos6502TargetInfo.cpp b/lib/Target/Mos6502/TargetInfo/Mos6502TargetInfo.cpp
index c9566ff397c..dd7be91f89f 100644
--- a/lib/Target/Mos6502/TargetInfo/Mos6502TargetInfo.cpp
+++ b/lib/Target/Mos6502/TargetInfo/Mos6502TargetInfo.cpp
@@ -10,17 +10,12 @@
 #include "Mos6502.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/TargetRegistry.h"
+
 using namespace llvm;
 
 Target llvm::TheMos6502Target;
-Target llvm::TheMos6502V9Target;
-Target llvm::TheMos6502elTarget;
 
 extern "C" void LLVMInitializeMos6502TargetInfo() {
-  RegisterTarget<Triple::mos6502, /*HasJIT=*/true> X(TheMos6502Target, "mos6502",
-                                                   "Mos6502");
-  RegisterTarget<Triple::mos6502v9, /*HasJIT=*/true> Y(TheMos6502V9Target,
-                                                     "mos6502v9", "Mos6502 V9");
-  RegisterTarget<Triple::mos6502el, /*HasJIT=*/true> Z(TheMos6502elTarget,
-                                                     "mos6502el", "Mos6502 LE");
+  RegisterTarget<Triple::mos6502, /*HasJIT=*/true> Z(TheMos6502Target,
+                                                     "mos6502", "Mos6502");
 }