mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Encode VFP arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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35275f499a
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@ -120,6 +120,8 @@ namespace {
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void emitMiscBranchInstruction(const MachineInstr &MI);
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void emitVFPArithInstruction(const MachineInstr &MI);
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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@ -313,6 +315,11 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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case ARMII::BrMiscFrm:
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emitMiscBranchInstruction(MI);
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break;
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// VFP instructions.
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case ARMII::VFPUnaryFrm:
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case ARMII::VFPBinaryFrm:
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emitVFPArithInstruction(MI);
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break;
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}
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}
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@ -976,4 +983,42 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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unsigned OpIdx = 0;
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assert((Binary & ARMII::D_BitShift) == 0 &&
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(Binary & ARMII::N_BitShift) == 0 &&
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(Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
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// Encode Dd / Sd.
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unsigned RegD = getMachineOpValue(MI, OpIdx++);
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Binary |= (RegD & 0x0f) << ARMII::RegFdShift;
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Binary |= (RegD & 0x10) << ARMII::D_BitShift;
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// If this is a two-address operand, skip it, e.g. FMACD.
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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++OpIdx;
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// Encode Dn / Sn.
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if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
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unsigned RegN = getMachineOpValue(MI, OpIdx++);
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Binary |= (RegN & 0x0f);
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Binary |= (RegN & 0x10) << ARMII::N_BitShift;
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}
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// Encode Dm / Sm.
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unsigned RegM = getMachineOpValue(MI, OpIdx++);
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Binary |= (RegM & 0x0f);
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Binary |= (RegM & 0x10) << ARMII::M_BitShift;
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emitWordLE(Binary);
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}
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#include "ARMGenCodeEmitter.inc"
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@ -36,8 +36,10 @@ def StMulFrm : Format<12>;
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def ArithMiscFrm: Format<13>;
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def ExtFrm : Format<14>;
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def ThumbFrm : Format<15>;
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def VFPFrm : Format<16>;
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def VFPFrm : Format<15>;
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def VFPUnaryFrm : Format<16>;
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def VFPBinaryFrm: Format<17>;
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def ThumbFrm : Format<18>;
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// Misc flag for data processing instructions that indicates whether
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// the instruction has a Rn register operand.
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@ -728,6 +730,100 @@ class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM VFP Instruction templates.
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//
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// ARM Float Instruction
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class ASI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPFrm, opc, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ASI5<dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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// ARM Double Instruction
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class ADI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPFrm, opc, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ADI5<dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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// Double precision, unary
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class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
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string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{19-16} = opcod2;
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let Inst{11-8} = 0b1011;
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let Inst{7-4} = opcod3;
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}
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// Double precision, binary
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class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
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let Inst{27-20} = opcod;
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let Inst{11-8} = 0b1011;
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}
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// Single precision, unary
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class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
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string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
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// Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
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let Inst{27-20} = opcod1;
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let Inst{19-16} = opcod2;
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let Inst{11-8} = 0b1010;
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let Inst{7-4} = opcod3;
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}
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// Single precision, binary
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class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
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// Bit 22 (D bit) can be changed during instruction encoding.
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let Inst{27-20} = opcod;
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let Inst{11-8} = 0b1010;
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}
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// Special cases.
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class AXSI<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXDI<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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//===----------------------------------------------------------------------===//
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@ -100,26 +100,33 @@ namespace ARMII {
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// Extend instructions
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ExtFrm = 14 << FormShift,
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// Thumb format
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ThumbFrm = 15 << FormShift,
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// VFP formats
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VPFFrm = 15 << FormShift,
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VFPUnaryFrm = 16 << FormShift,
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VFPBinaryFrm = 17 << FormShift,
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// VFP format
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VPFFrm = 16 << FormShift,
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// Thumb format
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ThumbFrm = 18 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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M_BitShift = 5,
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ShiftShift = 7,
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N_BitShift = 7,
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegFdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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RegFnShift = 16,
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S_BitShift = 20,
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W_BitShift = 21,
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AM3_I_BitShift = 22,
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D_BitShift = 22,
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U_BitShift = 23,
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P_BitShift = 24,
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I_BitShift = 25,
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@ -11,60 +11,6 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM VFP Instruction templates.
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//
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// ARM Float Instruction
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class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
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: AI<outs, ins, VFPFrm, opc, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
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: I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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// ARM Double Instruction
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class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
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: AI<outs, ins, VFPFrm, opc, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
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: I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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// Special cases.
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class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
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: XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
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: XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
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: XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
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: XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
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VFPFrm, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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def SDT_FTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF :
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@ -75,14 +21,14 @@ def SDT_FMDRR :
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SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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@ -140,45 +86,55 @@ def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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// FP Binary Operations.
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//
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def FADDD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
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def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"faddd", " $dst, $a, $b",
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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def FADDS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def FADDS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fadds", " $dst, $a, $b",
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[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
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def FCMPED : ADI<(outs), (ins DPR:$a, DPR:$b),
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def FCMPED : ADbI<0b11101011, (outs), (ins DPR:$a, DPR:$b),
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"fcmped", " $a, $b",
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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[(arm_cmpfp DPR:$a, DPR:$b)]> {
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let Inst{19-16} = 0b0100;
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let Inst{7-6} = 0b11;
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}
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def FCMPES : ASI<(outs), (ins SPR:$a, SPR:$b),
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def FCMPES : ASbI<0b11101011, (outs), (ins SPR:$a, SPR:$b),
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"fcmpes", " $a, $b",
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[(arm_cmpfp SPR:$a, SPR:$b)]>;
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[(arm_cmpfp SPR:$a, SPR:$b)]> {
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let Inst{19-16} = 0b0100;
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let Inst{7-6} = 0b11;
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}
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def FDIVD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
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def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fdivd", " $dst, $a, $b",
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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def FDIVS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fdivs", " $dst, $a, $b",
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[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
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def FMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
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def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fmuld", " $dst, $a, $b",
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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def FMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def FMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fmuls", " $dst, $a, $b",
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[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
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def FNMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
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def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fnmuld", " $dst, $a, $b",
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
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let Inst{6} = 1;
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}
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def FNMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fnmuls", " $dst, $a, $b",
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
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let Inst{6} = 1;
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}
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), DPR:$b),
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@ -187,11 +143,11 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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(FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def FSUBD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
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def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fsubd", " $dst, $a, $b",
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
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def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def FSUBS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fsubs", " $dst, $a, $b",
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[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
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@ -199,49 +155,55 @@ def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
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// FP Unary Operations.
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//
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def FABSD : ADI<(outs DPR:$dst), (ins DPR:$a),
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def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
|
||||
"fabsd", " $dst, $a",
|
||||
[(set DPR:$dst, (fabs DPR:$a))]>;
|
||||
|
||||
def FABSS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
||||
def FABSS : ASuI<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
|
||||
"fabss", " $dst, $a",
|
||||
[(set SPR:$dst, (fabs SPR:$a))]>;
|
||||
|
||||
def FCMPEZD : ADI<(outs), (ins DPR:$a),
|
||||
def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
|
||||
"fcmpezd", " $a",
|
||||
[(arm_cmpfp0 DPR:$a)]>;
|
||||
|
||||
def FCMPEZS : ASI<(outs), (ins SPR:$a),
|
||||
def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
|
||||
"fcmpezs", " $a",
|
||||
[(arm_cmpfp0 SPR:$a)]>;
|
||||
|
||||
def FCVTDS : ADI<(outs DPR:$dst), (ins SPR:$a),
|
||||
def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
|
||||
"fcvtds", " $dst, $a",
|
||||
[(set DPR:$dst, (fextend SPR:$a))]>;
|
||||
|
||||
def FCVTSD : ADI<(outs SPR:$dst), (ins DPR:$a),
|
||||
// Special case encoding: bits 11-8 is 0b1011.
|
||||
def FCVTSD : AI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
|
||||
"fcvtsd", " $dst, $a",
|
||||
[(set SPR:$dst, (fround DPR:$a))]>;
|
||||
[(set SPR:$dst, (fround DPR:$a))]> {
|
||||
let Inst{27-23} = 0b11101;
|
||||
let Inst{21-16} = 0b110111;
|
||||
let Inst{11-8} = 0b1011;
|
||||
let Inst{7-4} = 0b1100;
|
||||
}
|
||||
|
||||
def FCPYD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
||||
def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
|
||||
"fcpyd", " $dst, $a", []>;
|
||||
|
||||
def FCPYS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
||||
def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
|
||||
"fcpys", " $dst, $a", []>;
|
||||
|
||||
def FNEGD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
||||
def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
|
||||
"fnegd", " $dst, $a",
|
||||
[(set DPR:$dst, (fneg DPR:$a))]>;
|
||||
|
||||
def FNEGS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
||||
def FNEGS : ASuI<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
|
||||
"fnegs", " $dst, $a",
|
||||
[(set SPR:$dst, (fneg SPR:$a))]>;
|
||||
|
||||
def FSQRTD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
||||
def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
|
||||
"fsqrtd", " $dst, $a",
|
||||
[(set DPR:$dst, (fsqrt DPR:$a))]>;
|
||||
|
||||
def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
||||
def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
|
||||
"fsqrts", " $dst, $a",
|
||||
[(set SPR:$dst, (fsqrt SPR:$a))]>;
|
||||
|
||||
@ -323,45 +285,53 @@ def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
||||
// FP FMA Operations.
|
||||
//
|
||||
|
||||
def FMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
"fmacd", " $dst, $a, $b",
|
||||
[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
|
||||
def FMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
def FMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
"fmacs", " $dst, $a, $b",
|
||||
[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
|
||||
def FMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
"fmscd", " $dst, $a, $b",
|
||||
[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
|
||||
def FMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
"fmscs", " $dst, $a, $b",
|
||||
[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
|
||||
def FNMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
"fnmacd", " $dst, $a, $b",
|
||||
[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
RegConstraint<"$dstin = $dst"> {
|
||||
let Inst{6} = 1;
|
||||
}
|
||||
|
||||
def FNMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
def FNMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
"fnmacs", " $dst, $a, $b",
|
||||
[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
RegConstraint<"$dstin = $dst"> {
|
||||
let Inst{6} = 1;
|
||||
}
|
||||
|
||||
def FNMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
||||
"fnmscd", " $dst, $a, $b",
|
||||
[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
RegConstraint<"$dstin = $dst"> {
|
||||
let Inst{6} = 1;
|
||||
}
|
||||
|
||||
def FNMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
||||
"fnmscs", " $dst, $a, $b",
|
||||
[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
||||
RegConstraint<"$dstin = $dst">;
|
||||
RegConstraint<"$dstin = $dst"> {
|
||||
let Inst{6} = 1;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP Conditional moves.
|
||||
|
Loading…
Reference in New Issue
Block a user