mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matheus Almeida
parent
e89c50acc8
commit
9672a89c71
@ -22,26 +22,54 @@ class PseudoMSA<dag outs, dag ins, list<dag> pattern,
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}
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class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<3> m;
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let Inst{25-23} = major;
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let Inst{22-19} = 0b1110;
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let Inst{18-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<4> m;
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let Inst{25-23} = major;
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let Inst{22-20} = 0b110;
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let Inst{19-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<5> m;
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let Inst{25-23} = major;
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let Inst{22-21} = 0b10;
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let Inst{20-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<6> m;
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let Inst{25-23} = major;
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let Inst{22} = 0b0;
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let Inst{21-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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@ -1025,53 +1025,53 @@ class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
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// Instruction desc.
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class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCWS = RCWD,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm3:$u3);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u3");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt3:$u3))];
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm3:$m);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
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InstrItinClass Itinerary = itin;
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}
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class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCWS = RCWD,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm4:$u4);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u4");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt4:$u4))];
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm4:$m);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
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InstrItinClass Itinerary = itin;
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}
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class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCWS = RCWD,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm5:$u5);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u5");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt5:$u5))];
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm5:$m);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
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InstrItinClass Itinerary = itin;
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}
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class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCWS = RCWD,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm6:$u6);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u6");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt6:$u6))];
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm6:$m);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
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InstrItinClass Itinerary = itin;
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}
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class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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SplatComplexPattern SplatImm, RegisterClass RCWD,
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RegisterClass RCWS = RCWD,
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SplatComplexPattern SplatImm,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$u);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, SplatImm:$u))];
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
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InstrItinClass Itinerary = itin;
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}
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@ -1430,10 +1430,14 @@ class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", int_mips_bclr_h, MSA128HOpnd>;
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class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>;
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class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>;
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class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b, MSA128B>;
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class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h, MSA128H>;
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class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w, MSA128W>;
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class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d, MSA128D>;
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class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b,
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MSA128BOpnd>;
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class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h,
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MSA128HOpnd>;
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class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w,
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MSA128WOpnd>;
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class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d,
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MSA128DOpnd>;
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class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>;
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class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>;
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@ -1441,13 +1445,13 @@ class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>;
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class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>;
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class BINSLI_B_DESC : MSA_BIT_B_DESC_BASE<"binsli.b", int_mips_binsli_b,
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MSA128B>;
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MSA128BOpnd>;
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class BINSLI_H_DESC : MSA_BIT_H_DESC_BASE<"binsli.h", int_mips_binsli_h,
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MSA128H>;
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MSA128HOpnd>;
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class BINSLI_W_DESC : MSA_BIT_W_DESC_BASE<"binsli.w", int_mips_binsli_w,
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MSA128W>;
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MSA128WOpnd>;
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class BINSLI_D_DESC : MSA_BIT_D_DESC_BASE<"binsli.d", int_mips_binsli_d,
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MSA128D>;
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MSA128DOpnd>;
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class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>;
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class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>;
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@ -1455,13 +1459,13 @@ class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>;
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class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>;
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class BINSRI_B_DESC : MSA_BIT_B_DESC_BASE<"binsri.b", int_mips_binsri_b,
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MSA128B>;
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MSA128BOpnd>;
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class BINSRI_H_DESC : MSA_BIT_H_DESC_BASE<"binsri.h", int_mips_binsri_h,
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MSA128H>;
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MSA128HOpnd>;
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class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w,
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MSA128W>;
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MSA128WOpnd>;
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class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d,
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MSA128D>;
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MSA128DOpnd>;
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class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128BOpnd>;
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@ -1477,10 +1481,14 @@ class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128HOpnd>;
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class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", int_mips_bneg_w, MSA128WOpnd>;
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class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", int_mips_bneg_d, MSA128DOpnd>;
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class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b, MSA128B>;
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class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h, MSA128H>;
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class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w, MSA128W>;
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class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d, MSA128D>;
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class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b,
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MSA128BOpnd>;
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class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h,
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MSA128HOpnd>;
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class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w,
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MSA128WOpnd>;
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class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
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MSA128DOpnd>;
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class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128B>;
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class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128H>;
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@ -1518,10 +1526,14 @@ class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", int_mips_bset_h, MSA128HOpnd>;
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class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", int_mips_bset_w, MSA128WOpnd>;
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class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", int_mips_bset_d, MSA128DOpnd>;
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class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b, MSA128B>;
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class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h, MSA128H>;
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class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w, MSA128W>;
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class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d, MSA128D>;
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class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b,
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MSA128BOpnd>;
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class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h,
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MSA128HOpnd>;
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class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w,
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MSA128WOpnd>;
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class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d,
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MSA128DOpnd>;
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class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128B>;
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class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128H>;
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@ -2204,15 +2216,23 @@ class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
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class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
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class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
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class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b, MSA128B>;
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class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h, MSA128H>;
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class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w, MSA128W>;
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class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d, MSA128D>;
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class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
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MSA128BOpnd>;
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class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
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MSA128HOpnd>;
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class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
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MSA128WOpnd>;
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class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
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MSA128DOpnd>;
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class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b, MSA128B>;
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class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h, MSA128H>;
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class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w, MSA128W>;
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class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d, MSA128D>;
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class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
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MSA128BOpnd>;
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class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
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MSA128HOpnd>;
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class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
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MSA128WOpnd>;
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class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
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MSA128DOpnd>;
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class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
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class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
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@ -2234,13 +2254,13 @@ class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
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class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
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class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
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MSA128B>;
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MSA128BOpnd>;
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class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
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MSA128H>;
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MSA128HOpnd>;
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class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
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MSA128W>;
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MSA128WOpnd>;
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class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
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MSA128D>;
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MSA128DOpnd>;
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class SPLAT_B_DESC : MSA_3R_DESC_BASE<"splat.b", int_mips_splat_b, MSA128BOpnd,
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MSA128BOpnd, GPR32Opnd>;
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@ -2266,23 +2286,27 @@ class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
|
||||
class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
|
||||
|
||||
class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
|
||||
MSA128B>;
|
||||
MSA128BOpnd>;
|
||||
class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
|
||||
MSA128H>;
|
||||
MSA128HOpnd>;
|
||||
class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
|
||||
MSA128W>;
|
||||
MSA128WOpnd>;
|
||||
class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
|
||||
MSA128D>;
|
||||
MSA128DOpnd>;
|
||||
|
||||
class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
|
||||
class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
|
||||
class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
|
||||
class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
|
||||
|
||||
class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b, MSA128B>;
|
||||
class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h, MSA128H>;
|
||||
class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w, MSA128W>;
|
||||
class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d, MSA128D>;
|
||||
class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
|
||||
MSA128BOpnd>;
|
||||
class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
|
||||
MSA128HOpnd>;
|
||||
class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
|
||||
MSA128WOpnd>;
|
||||
class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
|
||||
MSA128DOpnd>;
|
||||
|
||||
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
|
||||
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
|
||||
@ -2290,23 +2314,27 @@ class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
|
||||
class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
|
||||
|
||||
class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
|
||||
MSA128B>;
|
||||
MSA128BOpnd>;
|
||||
class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
|
||||
MSA128H>;
|
||||
MSA128HOpnd>;
|
||||
class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
|
||||
MSA128W>;
|
||||
MSA128WOpnd>;
|
||||
class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
|
||||
MSA128D>;
|
||||
MSA128DOpnd>;
|
||||
|
||||
class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
|
||||
class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
|
||||
class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
|
||||
class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
|
||||
|
||||
class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b, MSA128B>;
|
||||
class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h, MSA128H>;
|
||||
class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w, MSA128W>;
|
||||
class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d, MSA128D>;
|
||||
class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
|
||||
MSA128BOpnd>;
|
||||
class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
|
||||
MSA128HOpnd>;
|
||||
class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
|
||||
MSA128WOpnd>;
|
||||
class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
|
||||
MSA128DOpnd>;
|
||||
|
||||
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem,
|
||||
|
||||
150
test/MC/Mips/msa/test_bit.s
Normal file
150
test/MC/Mips/msa/test_bit.s
Normal file
@ -0,0 +1,150 @@
|
||||
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
|
||||
#
|
||||
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
|
||||
#
|
||||
# CHECK: bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49]
|
||||
# CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09]
|
||||
# CHECK: bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9]
|
||||
# CHECK: bclri.d $w9, $w11, 0 # encoding: [0x79,0x80,0x5a,0x49]
|
||||
# CHECK: binsli.b $w25, $w12, 1 # encoding: [0x7b,0x71,0x66,0x49]
|
||||
# CHECK: binsli.h $w21, $w22, 0 # encoding: [0x7b,0x60,0xb5,0x49]
|
||||
# CHECK: binsli.w $w22, $w4, 0 # encoding: [0x7b,0x40,0x25,0x89]
|
||||
# CHECK: binsli.d $w6, $w2, 6 # encoding: [0x7b,0x06,0x11,0x89]
|
||||
# CHECK: binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9]
|
||||
# CHECK: binsri.h $w8, $w30, 1 # encoding: [0x7b,0xe1,0xf2,0x09]
|
||||
# CHECK: binsri.w $w2, $w19, 5 # encoding: [0x7b,0xc5,0x98,0x89]
|
||||
# CHECK: binsri.d $w18, $w20, 1 # encoding: [0x7b,0x81,0xa4,0x89]
|
||||
# CHECK: bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09]
|
||||
# CHECK: bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09]
|
||||
# CHECK: bnegi.w $w1, $w27, 5 # encoding: [0x7a,0xc5,0xd8,0x49]
|
||||
# CHECK: bnegi.d $w4, $w21, 1 # encoding: [0x7a,0x81,0xa9,0x09]
|
||||
# CHECK: bseti.b $w18, $w8, 0 # encoding: [0x7a,0x70,0x44,0x89]
|
||||
# CHECK: bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09]
|
||||
# CHECK: bseti.w $w9, $w18, 4 # encoding: [0x7a,0x44,0x92,0x49]
|
||||
# CHECK: bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9]
|
||||
# CHECK: sat_s.b $w31, $w31, 2 # encoding: [0x78,0x72,0xff,0xca]
|
||||
# CHECK: sat_s.h $w19, $w19, 0 # encoding: [0x78,0x60,0x9c,0xca]
|
||||
# CHECK: sat_s.w $w19, $w29, 0 # encoding: [0x78,0x40,0xec,0xca]
|
||||
# CHECK: sat_s.d $w11, $w22, 0 # encoding: [0x78,0x00,0xb2,0xca]
|
||||
# CHECK: sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a]
|
||||
# CHECK: sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a]
|
||||
# CHECK: sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca]
|
||||
# CHECK: sat_u.d $w29, $w16, 5 # encoding: [0x78,0x85,0x87,0x4a]
|
||||
# CHECK: slli.b $w23, $w10, 1 # encoding: [0x78,0x71,0x55,0xc9]
|
||||
# CHECK: slli.h $w9, $w18, 1 # encoding: [0x78,0x61,0x92,0x49]
|
||||
# CHECK: slli.w $w11, $w29, 4 # encoding: [0x78,0x44,0xea,0xc9]
|
||||
# CHECK: slli.d $w25, $w20, 1 # encoding: [0x78,0x01,0xa6,0x49]
|
||||
# CHECK: srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09]
|
||||
# CHECK: srai.h $w1, $w6, 0 # encoding: [0x78,0xe0,0x30,0x49]
|
||||
# CHECK: srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9]
|
||||
# CHECK: srai.d $w20, $w25, 3 # encoding: [0x78,0x83,0xcd,0x09]
|
||||
# CHECK: srari.b $w5, $w25, 0 # encoding: [0x79,0x70,0xc9,0x4a]
|
||||
# CHECK: srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca]
|
||||
# CHECK: srari.w $w17, $w11, 5 # encoding: [0x79,0x45,0x5c,0x4a]
|
||||
# CHECK: srari.d $w21, $w25, 5 # encoding: [0x79,0x05,0xcd,0x4a]
|
||||
# CHECK: srli.b $w2, $w0, 2 # encoding: [0x79,0x72,0x00,0x89]
|
||||
# CHECK: srli.h $w31, $w31, 2 # encoding: [0x79,0x62,0xff,0xc9]
|
||||
# CHECK: srli.w $w5, $w9, 4 # encoding: [0x79,0x44,0x49,0x49]
|
||||
# CHECK: srli.d $w27, $w26, 5 # encoding: [0x79,0x05,0xd6,0xc9]
|
||||
# CHECK: srlri.b $w18, $w3, 0 # encoding: [0x79,0xf0,0x1c,0x8a]
|
||||
# CHECK: srlri.h $w1, $w2, 3 # encoding: [0x79,0xe3,0x10,0x4a]
|
||||
# CHECK: srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca]
|
||||
# CHECK: srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a]
|
||||
|
||||
# CHECKOBJDUMP: bclri.b $w21, $w30, 2
|
||||
# CHECKOBJDUMP: bclri.h $w24, $w21, 0
|
||||
# CHECKOBJDUMP: bclri.w $w23, $w30, 3
|
||||
# CHECKOBJDUMP: bclri.d $w9, $w11, 0
|
||||
# CHECKOBJDUMP: binsli.b $w25, $w12, 1
|
||||
# CHECKOBJDUMP: binsli.h $w21, $w22, 0
|
||||
# CHECKOBJDUMP: binsli.w $w22, $w4, 0
|
||||
# CHECKOBJDUMP: binsli.d $w6, $w2, 6
|
||||
# CHECKOBJDUMP: binsri.b $w15, $w19, 0
|
||||
# CHECKOBJDUMP: binsri.h $w8, $w30, 1
|
||||
# CHECKOBJDUMP: binsri.w $w2, $w19, 5
|
||||
# CHECKOBJDUMP: binsri.d $w18, $w20, 1
|
||||
# CHECKOBJDUMP: bnegi.b $w24, $w19, 0
|
||||
# CHECKOBJDUMP: bnegi.h $w28, $w11, 3
|
||||
# CHECKOBJDUMP: bnegi.w $w1, $w27, 5
|
||||
# CHECKOBJDUMP: bnegi.d $w4, $w21, 1
|
||||
# CHECKOBJDUMP: bseti.b $w18, $w8, 0
|
||||
# CHECKOBJDUMP: bseti.h $w24, $w14, 2
|
||||
# CHECKOBJDUMP: bseti.w $w9, $w18, 4
|
||||
# CHECKOBJDUMP: bseti.d $w7, $w15, 1
|
||||
# CHECKOBJDUMP: sat_s.b $w31, $w31, 2
|
||||
# CHECKOBJDUMP: sat_s.h $w19, $w19, 0
|
||||
# CHECKOBJDUMP: sat_s.w $w19, $w29, 0
|
||||
# CHECKOBJDUMP: sat_s.d $w11, $w22, 0
|
||||
# CHECKOBJDUMP: sat_u.b $w1, $w13, 3
|
||||
# CHECKOBJDUMP: sat_u.h $w30, $w24, 4
|
||||
# CHECKOBJDUMP: sat_u.w $w31, $w13, 0
|
||||
# CHECKOBJDUMP: sat_u.d $w29, $w16, 5
|
||||
# CHECKOBJDUMP: slli.b $w23, $w10, 1
|
||||
# CHECKOBJDUMP: slli.h $w9, $w18, 1
|
||||
# CHECKOBJDUMP: slli.w $w11, $w29, 4
|
||||
# CHECKOBJDUMP: slli.d $w25, $w20, 1
|
||||
# CHECKOBJDUMP: srai.b $w24, $w29, 1
|
||||
# CHECKOBJDUMP: srai.h $w1, $w6, 0
|
||||
# CHECKOBJDUMP: srai.w $w7, $w26, 1
|
||||
# CHECKOBJDUMP: srai.d $w20, $w25, 3
|
||||
# CHECKOBJDUMP: srari.b $w5, $w25, 0
|
||||
# CHECKOBJDUMP: srari.h $w7, $w6, 4
|
||||
# CHECKOBJDUMP: srari.w $w17, $w11, 5
|
||||
# CHECKOBJDUMP: srari.d $w21, $w25, 5
|
||||
# CHECKOBJDUMP: srli.b $w2, $w0, 2
|
||||
# CHECKOBJDUMP: srli.h $w31, $w31, 2
|
||||
# CHECKOBJDUMP: srli.w $w5, $w9, 4
|
||||
# CHECKOBJDUMP: srli.d $w27, $w26, 5
|
||||
# CHECKOBJDUMP: srlri.b $w18, $w3, 0
|
||||
# CHECKOBJDUMP: srlri.h $w1, $w2, 3
|
||||
# CHECKOBJDUMP: srlri.w $w11, $w22, 2
|
||||
# CHECKOBJDUMP: srlri.d $w24, $w10, 6
|
||||
|
||||
bclri.b $w21, $w30, 2
|
||||
bclri.h $w24, $w21, 0
|
||||
bclri.w $w23, $w30, 3
|
||||
bclri.d $w9, $w11, 0
|
||||
binsli.b $w25, $w12, 1
|
||||
binsli.h $w21, $w22, 0
|
||||
binsli.w $w22, $w4, 0
|
||||
binsli.d $w6, $w2, 6
|
||||
binsri.b $w15, $w19, 0
|
||||
binsri.h $w8, $w30, 1
|
||||
binsri.w $w2, $w19, 5
|
||||
binsri.d $w18, $w20, 1
|
||||
bnegi.b $w24, $w19, 0
|
||||
bnegi.h $w28, $w11, 3
|
||||
bnegi.w $w1, $w27, 5
|
||||
bnegi.d $w4, $w21, 1
|
||||
bseti.b $w18, $w8, 0
|
||||
bseti.h $w24, $w14, 2
|
||||
bseti.w $w9, $w18, 4
|
||||
bseti.d $w7, $w15, 1
|
||||
sat_s.b $w31, $w31, 2
|
||||
sat_s.h $w19, $w19, 0
|
||||
sat_s.w $w19, $w29, 0
|
||||
sat_s.d $w11, $w22, 0
|
||||
sat_u.b $w1, $w13, 3
|
||||
sat_u.h $w30, $w24, 4
|
||||
sat_u.w $w31, $w13, 0
|
||||
sat_u.d $w29, $w16, 5
|
||||
slli.b $w23, $w10, 1
|
||||
slli.h $w9, $w18, 1
|
||||
slli.w $w11, $w29, 4
|
||||
slli.d $w25, $w20, 1
|
||||
srai.b $w24, $w29, 1
|
||||
srai.h $w1, $w6, 0
|
||||
srai.w $w7, $w26, 1
|
||||
srai.d $w20, $w25, 3
|
||||
srari.b $w5, $w25, 0
|
||||
srari.h $w7, $w6, 4
|
||||
srari.w $w17, $w11, 5
|
||||
srari.d $w21, $w25, 5
|
||||
srli.b $w2, $w0, 2
|
||||
srli.h $w31, $w31, 2
|
||||
srli.w $w5, $w9, 4
|
||||
srli.d $w27, $w26, 5
|
||||
srlri.b $w18, $w3, 0
|
||||
srlri.h $w1, $w2, 3
|
||||
srlri.w $w11, $w22, 2
|
||||
srlri.d $w24, $w10, 6
|
||||
Loading…
Reference in New Issue
Block a user