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Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).

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Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner 2010-11-18 22:06:46 +00:00
parent 24d22d2764
commit 9684a7c128
2 changed files with 10 additions and 1 deletions
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3
lib/Target/ARM/ARMISelLowering.cpp
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@ -4985,7 +4985,8 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
// Nothing to be done for scalar shifts.
if (! VT.isVector())
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (!VT.isVector() || !TLI.isTypeLegal(VT))
return SDValue();
assert(ST->hasNEON() && "unexpected vector shift");

8
test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llc < %s -march=arm -mattr=+neon
define void @lshrIllegalType(<8 x i32>* %A) nounwind {
%tmp1 = load <8 x i32>* %A
%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
store <8 x i32> %tmp2, <8 x i32>* %A
ret void
}