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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 17:32:19 +00:00
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3d5ed2250e
commit
969ba287cd
@ -9342,6 +9342,18 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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case Intrinsic::x86_avx2_pcmpgt_q:
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return DAG.getNode(X86ISD::PCMPGT, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_ssse3_pshuf_b_128:
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case Intrinsic::x86_avx2_pshuf_b:
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return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_ssse3_psign_b_128:
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case Intrinsic::x86_ssse3_psign_w_128:
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case Intrinsic::x86_ssse3_psign_d_128:
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case Intrinsic::x86_avx2_psign_b:
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case Intrinsic::x86_avx2_psign_w:
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case Intrinsic::x86_avx2_psign_d:
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return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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// ptest and testp intrinsics. The intrinsic these come from are designed to
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// return an integer value, not just an instruction so lower it to the ptest
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@ -48,7 +48,7 @@ def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
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def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86andnp : SDNode<"X86ISD::ANDNP",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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@ -741,10 +741,10 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
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{ X86::PORrr, X86::PORrm, TB_ALIGN_16 },
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{ X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
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{ X86::PSHUFBrr128, X86::PSHUFBrm128, TB_ALIGN_16 },
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{ X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
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{ X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
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{ X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
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{ X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
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{ X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
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{ X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
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{ X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
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{ X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
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{ X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
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{ X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
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@ -927,10 +927,10 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
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{ X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
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{ X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
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{ X86::VPSHUFBrr128, X86::VPSHUFBrm128, TB_ALIGN_16 },
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{ X86::VPSIGNBrr128, X86::VPSIGNBrm128, TB_ALIGN_16 },
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{ X86::VPSIGNWrr128, X86::VPSIGNWrm128, TB_ALIGN_16 },
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{ X86::VPSIGNDrr128, X86::VPSIGNDrm128, TB_ALIGN_16 },
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{ X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 },
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{ X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 },
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{ X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 },
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{ X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 },
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{ X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
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{ X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
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{ X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
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@ -1069,10 +1069,10 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
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{ X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
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{ X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
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{ X86::VPSHUFBrr256, X86::VPSHUFBrm256, TB_ALIGN_32 },
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{ X86::VPSIGNBrr256, X86::VPSIGNBrm256, TB_ALIGN_32 },
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{ X86::VPSIGNWrr256, X86::VPSIGNWrm256, TB_ALIGN_32 },
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{ X86::VPSIGNDrr256, X86::VPSIGNDrm256, TB_ALIGN_32 },
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{ X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 },
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{ X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 },
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{ X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 },
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{ X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 },
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{ X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
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{ X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
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{ X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
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@ -5148,20 +5148,20 @@ let isCommutable = 0 in {
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
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memopv2i64, i128mem, 0>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
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int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
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int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb",
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int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb",
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int_x86_ssse3_psign_b_128, 0>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw",
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int_x86_ssse3_psign_w_128, 0>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd",
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int_x86_ssse3_psign_d_128, 0>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
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int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
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@ -5177,20 +5177,20 @@ let isCommutable = 0 in {
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
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memopv4i64, i256mem, 0>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
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int_x86_avx2_phadd_sw>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
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int_x86_avx2_phsub_sw>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
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int_x86_avx2_pmadd_ub_sw>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb",
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int_x86_avx2_pshuf_b>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb",
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int_x86_avx2_psign_b>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw",
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int_x86_avx2_psign_w>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd",
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int_x86_avx2_psign_d>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
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int_x86_avx2_pmul_hr_sw>, VEX_4V;
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@ -5207,62 +5207,25 @@ let isCommutable = 0 in {
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memopv2i64, i128mem>;
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defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
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memopv2i64, i128mem>;
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defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
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memopv2i64, i128mem>;
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defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
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memopv2i64, i128mem>;
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defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
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memopv2i64, i128mem>;
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defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
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memopv2i64, i128mem>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb",
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb",
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw",
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd",
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int_x86_ssse3_psign_d_128>;
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}
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw_128>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(VPSHUFBrr128 VR128:$src, VR128:$mask)>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(VPSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
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def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
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}
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let Predicates = [HasSSSE3] in {
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Align Instruction Patterns
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//===---------------------------------------------------------------------===//
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