mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
MipsHi now has ouput flag
MipsAdd SDNode created to add support to an Add opcode which supports input flag Added an instruction itinerary to all instruction classes Added branches with zero cond codes Now call clobbers all non-callee saved registers Call w/ register support added Added DelaySlot to branch and load instructions Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41161 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
055c7eb4a4
commit
9710536b44
@ -26,9 +26,14 @@ def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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// handling 32-bit immediates. They are used on MipsISelLowering to
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// lower stuff like GlobalAddress, ExternalSymbol, ...
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// This two nodes have nothing to do with Mips Registers Hi and Lo.
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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// Necessary to generate glued instructions when loading GlobalAddress
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// into registers.
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def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
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SDNPAssociative, SDNPOptInFlag]>;
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// Return
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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@ -88,6 +93,11 @@ def immZExt16 : PatLeaf<(imm), [{
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return (uint64_t)N->getValue() == (unsigned short)N->getValue();
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}], LO16>;
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// Node immediate fits as 32-bit zero extended on target immediate.
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//def immZExt32 : PatLeaf<(imm), [{
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// return (uint64_t)N->getValue() == (uint32_t)N->getValue();
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//}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getValue() == ((N->getValue()) & 0x1f) ;
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@ -103,22 +113,23 @@ def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
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// Arithmetic 3 register operands
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let isCommutable = 1 in
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class ArithR< bits<6> op, bits<6> func, string instr_asm, SDNode OpNode>:
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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class ArithOverflowR< bits<6> op, bits<6> func, string instr_asm>:
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[]>;
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[], IIAlu>;
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// Arithmetic 2 register operands
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let isCommutable = 1 in
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@ -128,7 +139,7 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))] >;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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@ -138,7 +149,7 @@ class MArithR<bits<6> func, string instr_asm> :
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, " $rs, $rt"),
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[]>;
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[], IIImul>;
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// Logical
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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@ -147,14 +158,14 @@ class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))]>;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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@ -162,7 +173,7 @@ class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))] >;
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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let rt = 0 in
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@ -172,7 +183,7 @@ class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))] >;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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@ -180,7 +191,7 @@ class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm>:
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@ -188,16 +199,16 @@ class LoadUpper<bits<6> op, string instr_asm>:
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, " $dst, $imm"),
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[]>;
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[], IIAlu>;
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// Memory Load/Store
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let isLoad = 1 in
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let isLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))]>;
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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let isStore = 1 in
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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@ -205,17 +216,29 @@ class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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(outs),
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(ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)]>;
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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let isBranch = 1, isTerminator=1 in
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let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, " $a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)]>;
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, " $src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR< op,
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@ -223,7 +246,8 @@ class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))]>;
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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Operand Od, PatLeaf imm_type>:
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@ -231,52 +255,64 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>;
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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// Unconditional branch
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let hasCtrlDep=1, isTerminator=1 in
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let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFJ<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, " $target"),
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[(br bb:$target)]>;
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[(br bb:$target)], IIBranch>;
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let hasCtrlDep=1, isTerminator=1, rd=0 in
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$target),
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!strconcat(instr_asm, " $target"),
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[]>;
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[], IIBranch>;
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// Jump and Link (Call)
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let isCall=1 in
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target),
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!strconcat(instr_asm, " $target"),
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[(MipsJmpLink imm:$target)]>;
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
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T3, T4, T5, T6, T7, T8, T9, K0, K1, GP] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target),
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!strconcat(instr_asm, " $target"),
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[(MipsJmpLink imm:$target)], IIBranch>;
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let isCall=1 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$rd, CPURegs:$rs),
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!strconcat(instr_asm, " $rs, $rd"),
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[]>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$rs),
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!strconcat(instr_asm, " $rs"),
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[(MipsJmpLink CPURegs:$rs)], IIBranch>;
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class BranchLink<string instr_asm>:
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FI< 0x1,
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(outs),
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(ins CPURegs:$rs, brtarget:$target),
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!strconcat(instr_asm, " $rs, $target"),
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[], IIBranch>;
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}
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm>:
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, " $a, $b"),
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[]>;
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[], itin>;
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// Move from Hi/Lo
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class MoveFromTo<bits<6> func, string instr_asm>:
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@ -285,7 +321,7 @@ class MoveFromTo<bits<6> func, string instr_asm>:
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(outs CPURegs:$dst),
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(ins),
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!strconcat(instr_asm, " $dst"),
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[]>;
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[], IIHiLo>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm>:
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@ -294,15 +330,15 @@ class CountLeading<bits<6> func, string instr_asm>:
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(outs CPURegs:$dst),
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(ins CPURegs:$src),
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!strconcat(instr_asm, " $dst, $src"),
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[]>;
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[], IIAlu>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern>;
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt),
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@ -321,15 +357,18 @@ def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins),
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips32 I
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// MipsI Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic
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def ADDiu : ArithI<0x09, "addiu", add, uimm16, immSExt16>;
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def ADDi : ArithI<0x08, "addi", add, simm16, immZExt16>;
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def MUL : ArithR<0x1c, 0x02, "mul", mul>;
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def ADDu : ArithR<0x00, 0x21, "addu", add>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub>;
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// ADDiu just accept 16-bit immediates but we handle this on Pat's.
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// immZExt32 is used here so it can match GlobalAddress immediates.
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def ADDiu : ArithI<0x09, "addiu", MipsAdd, uimm16, immZExt16>;
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def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
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def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
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def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def ADD : ArithOverflowR<0x00, 0x20, "add">;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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def MADD : MArithR<0x00, "madd">;
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@ -370,6 +409,17 @@ def SW : StoreM<0x2b, "sw", store>;
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// Conditional Branch
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def BEQ : CBranch<0x04, "beq", seteq>;
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def BNE : CBranch<0x05, "bne", setne>;
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let rt=1 in
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def BGEZ : CBranchZero<0x01, "bgez", setge>;
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let rt=0 in {
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def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
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def BLEZ : CBranchZero<0x07, "blez", setle>;
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def BLTZ : CBranchZero<0x01, "bltz", setlt>;
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}
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// Set Condition Code
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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@ -382,14 +432,16 @@ def JR : JumpFR<0x00, 0x08, "jr">;
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// Jump and Link (Call)
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
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def BGEZAL : BranchLink<"bgezal">;
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def BLTZAL : BranchLink<"bltzal">;
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// MulDiv and Move From Hi/Lo operations, have
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// their correpondent SDNodes created on ISelDAG.
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// Special Mul, Div operations
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def MULT : MulDiv<0x18, "mult">;
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def MULTu : MulDiv<0x19, "multu">;
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def DIV : MulDiv<0x1a, "div">;
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def DIVu : MulDiv<0x1b, "divu">;
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def MULT : MulDiv<0x18, "mult", IIImul>;
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def MULTu : MulDiv<0x19, "multu", IIImul>;
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def DIV : MulDiv<0x1a, "div", IIIdiv>;
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def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
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// Move From Hi/Lo
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def MFHI : MoveFromTo<0x10, "mfhi">;
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@ -403,7 +455,7 @@ def CLZ : CountLeading<0x20, "clz">;
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// No operation
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let addr=0 in
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def NOOP : FJ<0, (outs), (ins), "nop", []>;
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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// Ret instruction - as mips does not have "ret" a
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// jr $ra must be generated.
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@ -411,7 +463,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1,
|
||||
isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
|
||||
{
|
||||
def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
|
||||
"jr $target", [(MipsRet CPURegs:$target)]>;
|
||||
"jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -433,59 +485,101 @@ def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
||||
(JAL tglobaladdr:$dst)>;
|
||||
def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
||||
(JAL texternalsym:$dst)>;
|
||||
def : Pat<(MipsJmpLink CPURegs:$dst),
|
||||
(JALR CPURegs:$dst)>;
|
||||
|
||||
// GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
|
||||
def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
||||
def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
||||
|
||||
// When extracting the address from GlobalAddress we
|
||||
// need something of the form "addiu $reg, %lo(addr)"
|
||||
def : Pat<(add CPURegs:$a, (MipsLo tglobaladdr:$in)),
|
||||
(ADDiu CPURegs:$a, tglobaladdr:$in)>;
|
||||
def : Pat<(MipsAdd CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
||||
|
||||
// Mips does not have not, so we increase the operation
|
||||
def : Pat<(not CPURegs:$in),
|
||||
(NOR CPURegs:$in, CPURegs:$in)>;
|
||||
(NOR CPURegs:$in, ZERO)>;
|
||||
|
||||
// extended load and stores
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
|
||||
def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
|
||||
(SB CPURegs:$src, addr:$src)>;
|
||||
(SB CPURegs:$src, addr:$addr)>;
|
||||
|
||||
def : Pat<(brcond (setne CPURegs:$lhs, (add ZERO, 0)), bb:$dst),
|
||||
///
|
||||
/// brcond patterns
|
||||
///
|
||||
|
||||
// direct match equal/notequal zero branches
|
||||
def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
|
||||
(BNE CPURegs:$lhs, ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
|
||||
(BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
|
||||
|
||||
|
||||
// Conditional branch patterns.
|
||||
// cond branches patterns, 2 register operands signed.
|
||||
def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
|
||||
// cond branches patterns, 2 register operands unsigned.
|
||||
def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
|
||||
(BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
(BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
|
||||
// cond branches patterns, reg/imm operands signed.
|
||||
def : Pat<(brcond (setult CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
|
||||
def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
|
||||
(BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
|
||||
(BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
|
||||
// cond branches patterns, reg/imm operands unsigned.
|
||||
def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
|
||||
(BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setuge CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
|
||||
(BEQ (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
||||
(BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
||||
|
||||
// generic brcond pattern
|
||||
def : Pat<(brcond CPURegs:$cond, bb:$dst),
|
||||
(BNE CPURegs:$cond, ZERO, bb:$dst)>;
|
||||
|
||||
///
|
||||
/// setcc patterns, only matched when there
|
||||
/// is no brcond following a setcc operation
|
||||
///
|
||||
|
||||
// setcc 2 register operands
|
||||
def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
|
||||
def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
|
||||
|
||||
def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs)>;
|
||||
def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLTu CPURegs:$rhs, CPURegs:$lhs)>;
|
||||
|
||||
def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
||||
def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
||||
|
||||
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
||||
(OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs))>;
|
||||
|
||||
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
|
||||
|
||||
// setcc reg/imm operands
|
||||
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
|
||||
(XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user