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https://github.com/c64scene-ar/llvm-6502.git
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[X86][FastIsel] Teach how to select vector load instructions.
This patch teaches fast-isel how to select 128-bit vector load instructions. Added test CodeGen/X86/fast-isel-vecload.ll Differential Revision: http://reviews.llvm.org/D8605 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233270 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
a977f7e771
commit
971eb1b382
@ -84,7 +84,7 @@ private:
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bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT, DebugLoc DL);
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bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, MachineMemOperand *MMO,
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unsigned &ResultReg);
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unsigned &ResultReg, unsigned Alignment = 1);
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bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
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MachineMemOperand *MMO = nullptr, bool Aligned = false);
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@ -327,7 +327,8 @@ bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
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/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
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/// Return true and the result register by reference if it is possible.
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bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
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MachineMemOperand *MMO, unsigned &ResultReg) {
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MachineMemOperand *MMO, unsigned &ResultReg,
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unsigned Alignment) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = nullptr;
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@ -372,6 +373,30 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
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case MVT::f80:
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// No f80 support yet.
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return false;
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case MVT::v4f32:
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if (Alignment >= 16)
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Opc = Subtarget->hasAVX() ? X86::VMOVAPSrm : X86::MOVAPSrm;
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else
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Opc = Subtarget->hasAVX() ? X86::VMOVUPSrm : X86::MOVUPSrm;
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RC = &X86::VR128RegClass;
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break;
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case MVT::v2f64:
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if (Alignment >= 16)
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Opc = Subtarget->hasAVX() ? X86::VMOVAPDrm : X86::MOVAPDrm;
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else
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Opc = Subtarget->hasAVX() ? X86::VMOVUPDrm : X86::MOVUPDrm;
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RC = &X86::VR128RegClass;
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break;
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v8i16:
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case MVT::v16i8:
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if (Alignment >= 16)
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Opc = Subtarget->hasAVX() ? X86::VMOVDQArm : X86::MOVDQArm;
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else
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Opc = Subtarget->hasAVX() ? X86::VMOVDQUrm : X86::MOVDQUrm;
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RC = &X86::VR128RegClass;
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break;
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}
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ResultReg = createResultReg(RC);
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@ -1068,8 +1093,14 @@ bool X86FastISel::X86SelectLoad(const Instruction *I) {
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if (!X86SelectAddress(Ptr, AM))
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return false;
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unsigned Alignment = LI->getAlignment();
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unsigned ABIAlignment = DL.getABITypeAlignment(LI->getType());
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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Alignment = ABIAlignment;
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unsigned ResultReg = 0;
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if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg))
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if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg,
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Alignment))
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return false;
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updateValueMap(I, ResultReg);
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185
test/CodeGen/X86/fast-isel-vecload.ll
Normal file
185
test/CodeGen/X86/fast-isel-vecload.ll
Normal file
@ -0,0 +1,185 @@
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; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE --check-prefix=ALL
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; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX --check-prefix=ALL
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; Verify that fast-isel knows how to select aligned/unaligned vector loads.
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; Also verify that the selected load instruction is in the correct domain.
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define <16 x i8> @test_v16i8(<16 x i8>* %V) {
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; ALL-LABEL: test_v16i8:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <16 x i8>, <16 x i8>* %V, align 16
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ret <16 x i8> %0
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}
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define <8 x i16> @test_v8i16(<8 x i16>* %V) {
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; ALL-LABEL: test_v8i16:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <8 x i16>, <8 x i16>* %V, align 16
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ret <8 x i16> %0
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}
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define <4 x i32> @test_v4i32(<4 x i32>* %V) {
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; ALL-LABEL: test_v4i32:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x i32>, <4 x i32>* %V, align 16
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ret <4 x i32> %0
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}
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define <2 x i64> @test_v2i64(<2 x i64>* %V) {
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; ALL-LABEL: test_v2i64:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x i64>, <2 x i64>* %V, align 16
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ret <2 x i64> %0
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}
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define <16 x i8> @test_v16i8_unaligned(<16 x i8>* %V) {
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; ALL-LABEL: test_v16i8_unaligned:
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; SSE: movdqu (%rdi), %xmm0
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; AVX: vmovdqu (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <16 x i8>, <16 x i8>* %V, align 4
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ret <16 x i8> %0
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}
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define <8 x i16> @test_v8i16_unaligned(<8 x i16>* %V) {
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; ALL-LABEL: test_v8i16_unaligned:
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; SSE: movdqu (%rdi), %xmm0
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; AVX: vmovdqu (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <8 x i16>, <8 x i16>* %V, align 4
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ret <8 x i16> %0
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}
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define <4 x i32> @test_v4i32_unaligned(<4 x i32>* %V) {
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; ALL-LABEL: test_v4i32_unaligned:
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; SSE: movdqu (%rdi), %xmm0
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; AVX: vmovdqu (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x i32>, <4 x i32>* %V, align 4
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ret <4 x i32> %0
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}
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define <2 x i64> @test_v2i64_unaligned(<2 x i64>* %V) {
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; ALL-LABEL: test_v2i64_unaligned:
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; SSE: movdqu (%rdi), %xmm0
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; AVX: vmovdqu (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x i64>, <2 x i64>* %V, align 4
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ret <2 x i64> %0
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}
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define <4 x float> @test_v4f32(<4 x float>* %V) {
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; ALL-LABEL: test_v4f32:
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; SSE: movaps (%rdi), %xmm0
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; AVX: vmovaps (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x float>, <4 x float>* %V, align 16
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ret <4 x float> %0
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}
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define <2 x double> @test_v2f64(<2 x double>* %V) {
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; ALL-LABEL: test_v2f64:
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; SSE: movapd (%rdi), %xmm0
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; AVX: vmovapd (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x double>, <2 x double>* %V, align 16
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ret <2 x double> %0
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}
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define <4 x float> @test_v4f32_unaligned(<4 x float>* %V) {
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; ALL-LABEL: test_v4f32_unaligned:
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; SSE: movups (%rdi), %xmm0
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; AVX: vmovups (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x float>, <4 x float>* %V, align 4
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ret <4 x float> %0
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}
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define <2 x double> @test_v2f64_unaligned(<2 x double>* %V) {
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; ALL-LABEL: test_v2f64_unaligned:
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; SSE: movupd (%rdi), %xmm0
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; AVX: vmovupd (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x double>, <2 x double>* %V, align 4
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ret <2 x double> %0
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}
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define <16 x i8> @test_v16i8_abi_alignment(<16 x i8>* %V) {
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; ALL-LABEL: test_v16i8_abi_alignment:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <16 x i8>, <16 x i8>* %V
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ret <16 x i8> %0
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}
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define <8 x i16> @test_v8i16_abi_alignment(<8 x i16>* %V) {
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; ALL-LABEL: test_v8i16_abi_alignment:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <8 x i16>, <8 x i16>* %V
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ret <8 x i16> %0
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}
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define <4 x i32> @test_v4i32_abi_alignment(<4 x i32>* %V) {
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; ALL-LABEL: test_v4i32_abi_alignment:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x i32>, <4 x i32>* %V
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ret <4 x i32> %0
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}
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define <2 x i64> @test_v2i64_abi_alignment(<2 x i64>* %V) {
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; ALL-LABEL: test_v2i64_abi_alignment:
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; SSE: movdqa (%rdi), %xmm0
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; AVX: vmovdqa (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x i64>, <2 x i64>* %V
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ret <2 x i64> %0
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}
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define <4 x float> @test_v4f32_abi_alignment(<4 x float>* %V) {
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; ALL-LABEL: test_v4f32_abi_alignment:
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; SSE: movaps (%rdi), %xmm0
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; AVX: vmovaps (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <4 x float>, <4 x float>* %V
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ret <4 x float> %0
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}
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define <2 x double> @test_v2f64_abi_alignment(<2 x double>* %V) {
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; ALL-LABEL: test_v2f64_abi_alignment:
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; SSE: movapd (%rdi), %xmm0
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; AVX: vmovapd (%rdi), %xmm0
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; ALL-NEXT: retq
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entry:
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%0 = load <2 x double>, <2 x double>* %V
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ret <2 x double> %0
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}
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