6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Custom lower f64 -> i64 conversions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219038 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-10-03 23:54:56 +00:00
parent ad2f641c33
commit 9747d27b59
7 changed files with 179 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -286,6 +286,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
if (!Subtarget->hasFFBH())
@ -558,6 +560,8 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
}
return Op;
}
@ -1865,6 +1869,55 @@ SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
return SDValue();
}
SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
bool Signed) const {
SDLoc SL(Op);
SDValue Src = Op.getOperand(0);
SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
SDValue K0
= DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
SDValue K1
= DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
MVT::i32, FloorMul);
SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
}
SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
SelectionDAG &DAG) const {
SDValue Src = Op.getOperand(0);
if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
return LowerFP64_TO_INT(Op, DAG, true);
return SDValue();
}
SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
SelectionDAG &DAG) const {
SDValue Src = Op.getOperand(0);
if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
return LowerFP64_TO_INT(Op, DAG, false);
return SDValue();
}
SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
unsigned BitsDiff,
SelectionDAG &DAG) const {

4
lib/Target/R600/AMDGPUISelLowering.h
View File

@ -55,6 +55,10 @@ private:
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
unsigned BitsDiff,
SelectionDAG &DAG) const;

3
lib/Target/R600/SIISelLowering.cpp
View File

@ -168,9 +168,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::LOAD, MVT::i1, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::FrameIndex, MVT::i32, Custom);

29
test/CodeGen/R600/fp64_to_sint.ll
View File

@ -1,29 +0,0 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}fp_to_sint_f64_i32:
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_f64_i32(i32 addrspace(1)* %out, double %in) {
%result = fptosi double %in to i32
store i32 %result, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}fp_to_sint_v2f64_v2i32:
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_v2f64_v2i32(<2 x i32> addrspace(1)* %out, <2 x double> %in) {
%result = fptosi <2 x double> %in to <2 x i32>
store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}fp_to_sint_v4f64_v4i32:
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> %in) {
%result = fptosi <4 x double> %in to <4 x i32>
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
}

56
test/CodeGen/R600/fp_to_sint.f64.ll Normal file
View File

@ -0,0 +1,56 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; FUNC-LABEL: @fp_to_sint_f64_i32
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_f64_i32(i32 addrspace(1)* %out, double %in) {
%result = fptosi double %in to i32
store i32 %result, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: @fp_to_sint_v2f64_v2i32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_v2f64_v2i32(<2 x i32> addrspace(1)* %out, <2 x double> %in) {
%result = fptosi <2 x double> %in to <2 x i32>
store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void
}
; FUNC-LABEL: @fp_to_sint_v4f64_v4i32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
; SI: V_CVT_I32_F64_e32
define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> %in) {
%result = fptosi <4 x double> %in to <4 x i32>
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
}
; FUNC-LABEL: @fp_to_sint_i64_f64
; CI-DAG: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; CI-DAG: V_TRUNC_F64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
; CI-DAG: S_MOV_B32 s[[K0_LO:[0-9]+]], 0{{$}}
; CI-DAG: S_MOV_B32 s[[K0_HI:[0-9]+]], 0x3df00000
; CI-DAG: V_MUL_F64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
; CI-DAG: V_FLOOR_F64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
; CI-DAG: S_MOV_B32 s[[K1_HI:[0-9]+]], 0xc1f00000
; CI-DAG: V_FMA_F64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
; CI-DAG: V_CVT_U32_F64_e32 v[[LO:[0-9]+]], [[FMA]]
; CI-DAG: V_CVT_I32_F64_e32 v[[HI:[0-9]+]], [[FLOOR]]
; CI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO]]:[[HI]]{{\]}}
define void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep = getelementptr double addrspace(1)* %in, i32 %tid
%val = load double addrspace(1)* %gep, align 8
%cast = fptosi double %val to i64
store i64 %cast, i64 addrspace(1)* %out, align 8
ret void
}

61
test/CodeGen/R600/fp_to_uint.f64.ll
View File

@ -1,4 +1,7 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; SI-LABEL: {{^}}fp_to_uint_i32_f64:
; SI: V_CVT_U32_F64_e32
@ -7,3 +10,61 @@ define void @fp_to_uint_i32_f64(i32 addrspace(1)* %out, double %in) {
store i32 %cast, i32 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @fp_to_uint_v2i32_v2f64
; SI: V_CVT_U32_F64_e32
; SI: V_CVT_U32_F64_e32
define void @fp_to_uint_v2i32_v2f64(<2 x i32> addrspace(1)* %out, <2 x double> %in) {
%cast = fptoui <2 x double> %in to <2 x i32>
store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8
ret void
}
; SI-LABEL: @fp_to_uint_v4i32_v4f64
; SI: V_CVT_U32_F64_e32
; SI: V_CVT_U32_F64_e32
; SI: V_CVT_U32_F64_e32
; SI: V_CVT_U32_F64_e32
define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> %in) {
%cast = fptoui <4 x double> %in to <4 x i32>
store <4 x i32> %cast, <4 x i32> addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: @fp_to_uint_i64_f64
; CI-DAG: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; CI-DAG: V_TRUNC_F64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
; CI-DAG: S_MOV_B32 s[[K0_LO:[0-9]+]], 0{{$}}
; CI-DAG: S_MOV_B32 s[[K0_HI:[0-9]+]], 0x3df00000
; CI-DAG: V_MUL_F64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
; CI-DAG: V_FLOOR_F64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
; CI-DAG: S_MOV_B32 s[[K1_HI:[0-9]+]], 0xc1f00000
; CI-DAG: V_FMA_F64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
; CI-DAG: V_CVT_U32_F64_e32 v[[LO:[0-9]+]], [[FMA]]
; CI-DAG: V_CVT_U32_F64_e32 v[[HI:[0-9]+]], [[FLOOR]]
; CI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO]]:[[HI]]{{\]}}
define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep = getelementptr double addrspace(1)* %in, i32 %tid
%val = load double addrspace(1)* %gep, align 8
%cast = fptoui double %val to i64
store i64 %cast, i64 addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: @fp_to_uint_v2i64_v2f64
define void @fp_to_uint_v2i64_v2f64(<2 x i64> addrspace(1)* %out, <2 x double> %in) {
%cast = fptoui <2 x double> %in to <2 x i64>
store <2 x i64> %cast, <2 x i64> addrspace(1)* %out, align 16
ret void
}
; SI-LABEL: @fp_to_uint_v4i64_v4f64
define void @fp_to_uint_v4i64_v4f64(<4 x i64> addrspace(1)* %out, <4 x double> %in) {
%cast = fptoui <4 x double> %in to <4 x i64>
store <4 x i64> %cast, <4 x i64> addrspace(1)* %out, align 32
ret void
}

10
test/CodeGen/R600/uint_to_fp.f64.ll
View File

@ -2,7 +2,7 @@
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; SI-LABEL: {{$}}uint_to_fp_f64_i32
; SI-LABEL: {{^}}uint_to_fp_f64_i32
; SI: V_CVT_F64_U32_e32
; SI: S_ENDPGM
define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) {
@ -37,7 +37,7 @@ define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
ret void
}
; SI-LABEL: {{$}}v_uint_to_fp_i64_to_f64
; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
; SI-DAG: V_CVT_F64_U32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
; SI-DAG: V_CVT_F64_U32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
@ -53,21 +53,21 @@ define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)
ret void
}
; SI-LABEL: {{$}}s_uint_to_fp_f64_i64
; SI-LABEL: {{^}}s_uint_to_fp_f64_i64
define void @s_uint_to_fp_f64_i64(double addrspace(1)* %out, i64 %in) {
%cast = uitofp i64 %in to double
store double %cast, double addrspace(1)* %out, align 8
ret void
}
; SI-LABEL: {{$}}s_uint_to_fp_v2f64_v2i64
; SI-LABEL: {{^}}s_uint_to_fp_v2f64_v2i64
define void @s_uint_to_fp_v2f64_v2i64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
%cast = uitofp <2 x i64> %in to <2 x double>
store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
ret void
}
; SI-LABEL: {{$}}s_uint_to_fp_v4f64_v4i64
; SI-LABEL: {{^}}s_uint_to_fp_v4f64_v4i64
define void @s_uint_to_fp_v4f64_v4i64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
%cast = uitofp <4 x i64> %in to <4 x double>
store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16