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Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-06-19 01:59:04 +00:00
parent 8ebf83b2cc
commit 974fe5d691
1 changed files with 20 additions and 15 deletions
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35
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -620,7 +620,7 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI, MachineBasicBlock::iterator &MBBI,
int OffImm, bool isDef, int OffImm, bool isDef,
DebugLoc dl, unsigned NewOpc, DebugLoc dl, unsigned NewOpc,
unsigned Reg, bool RegKill, unsigned Reg, bool RegDeadKill,
unsigned BaseReg, bool BaseKill, unsigned BaseReg, bool BaseKill,
unsigned OffReg, bool OffKill, unsigned OffReg, bool OffKill,
ARMCC::CondCodes Pred, unsigned PredReg, ARMCC::CondCodes Pred, unsigned PredReg,
@ -631,14 +631,15 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
else else
Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift); Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift);
if (isDef) if (isDef)
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc), Reg) BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
.addReg(BaseReg, getKillRegState(BaseKill)) .addReg(BaseReg, getKillRegState(BaseKill))
.addReg(OffReg, getKillRegState(OffKill)) .addReg(OffReg, getKillRegState(OffKill))
.addImm(Offset) .addImm(Offset)
.addImm(Pred).addReg(PredReg); .addImm(Pred).addReg(PredReg);
else else
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(Reg, getKillRegState(RegKill)) .addReg(Reg, getKillRegState(RegDeadKill))
.addReg(BaseReg, getKillRegState(BaseKill)) .addReg(BaseReg, getKillRegState(BaseKill))
.addReg(OffReg, getKillRegState(OffKill)) .addReg(OffReg, getKillRegState(OffKill))
.addImm(Offset) .addImm(Offset)
@ -658,8 +659,10 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
return false; return false;
bool isLd = Opcode == ARM::LDRD; bool isLd = Opcode == ARM::LDRD;
bool EvenKill = isLd ? false : MI->getOperand(0).isKill(); bool EvenDeadKill = isLd ?
bool OddKill = isLd ? false : MI->getOperand(1).isKill(); MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
bool OddDeadKill = isLd ?
MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
const MachineOperand &BaseOp = MI->getOperand(2); const MachineOperand &BaseOp = MI->getOperand(2);
unsigned BaseReg = BaseOp.getReg(); unsigned BaseReg = BaseOp.getReg();
bool BaseKill = BaseOp.isKill(); bool BaseKill = BaseOp.isKill();
@ -679,16 +682,16 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
.addReg(BaseReg, getKillRegState(BaseKill)) .addReg(BaseReg, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
.addImm(Pred).addReg(PredReg) .addImm(Pred).addReg(PredReg)
.addReg(EvenReg, getDefRegState(isLd)) .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
.addReg(OddReg, getDefRegState(isLd)); .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
++NumLDRD2LDM; ++NumLDRD2LDM;
} else { } else {
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(BaseReg, getKillRegState(BaseKill)) .addReg(BaseReg, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
.addImm(Pred).addReg(PredReg) .addImm(Pred).addReg(PredReg)
.addReg(EvenReg, getKillRegState(EvenKill)) .addReg(EvenReg, getKillRegState(EvenDeadKill))
.addReg(OddReg, getKillRegState(OddKill)); .addReg(OddReg, getKillRegState(OddDeadKill));
++NumSTRD2STM; ++NumSTRD2STM;
} }
} else { } else {
@ -703,15 +706,17 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
(OffReg && TRI->regsOverlap(EvenReg, OffReg)))) { (OffReg && TRI->regsOverlap(EvenReg, OffReg)))) {
assert(!TRI->regsOverlap(OddReg, BaseReg) && assert(!TRI->regsOverlap(OddReg, BaseReg) &&
(!OffReg || !TRI->regsOverlap(OddReg, OffReg))); (!OffReg || !TRI->regsOverlap(OddReg, OffReg)));
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, OddReg, OddKill, InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, OddReg, OddDeadKill,
BaseReg, false, OffReg, false, Pred, PredReg, TII); BaseReg, false, OffReg, false, Pred, PredReg, TII);
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, EvenReg, EvenKill, InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, EvenReg, EvenDeadKill,
BaseReg, BaseKill, OffReg, OffKill, Pred, PredReg, TII); BaseReg, BaseKill, OffReg, OffKill, Pred, PredReg, TII);
} else { } else {
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, EvenReg, EvenKill, InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
BaseReg, false, OffReg, false, Pred, PredReg, TII); EvenReg, EvenDeadKill, BaseReg, false, OffReg, false,
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, OddReg, OddKill, Pred, PredReg, TII);
BaseReg, BaseKill, OffReg, OffKill, Pred, PredReg, TII); InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
OddReg, OddDeadKill, BaseReg, BaseKill, OffReg, OffKill,
Pred, PredReg, TII);
} }
if (isLd) if (isLd)
++NumLDRD2LDR; ++NumLDRD2LDR;