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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
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Eric Christopher 2010-08-19 15:35:27 +00:00
parent 44cbde85ba
commit 979e0a1414
1 changed files with 1 additions and 1 deletions
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lib/Target/ARM/ARMFastISel.cpp
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@ -137,7 +137,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
// Do we optionally set a predicate? Preds is size > 0 iff the predicate // Do we optionally set a predicate? Preds is size > 0 iff the predicate
// defines CPSR. All other OptionalDefines in ARM are the CCR register. // defines CPSR. All other OptionalDefines in ARM are the CCR register.
bool CPSR; bool CPSR = false;
if (DefinesOptionalPredicate(MI, &CPSR)) { if (DefinesOptionalPredicate(MI, &CPSR)) {
if (CPSR) if (CPSR)
AddDefaultT1CC(MIB); AddDefaultT1CC(MIB);