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- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2

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instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-04-27 01:27:19 +00:00
parent 97b44f9b80
commit 97a454317a
3 changed files with 40 additions and 16 deletions
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12
lib/Target/ARM/ARMInstrThumb2.td
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@ -3017,7 +3017,7 @@ def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
"isb", "\t$opt", "isb", "\t$opt",
[]>, Requires<[IsThumb2, HasDB]> { []>, Requires<[IsThumb, HasDB]> {
bits<4> opt; bits<4> opt;
let Inst{31-4} = 0xf3bf8f6; let Inst{31-4} = 0xf3bf8f6;
let Inst{3-0} = opt; let Inst{3-0} = opt;
@ -3646,7 +3646,7 @@ def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
// the A/R class (a full msr_mask). // the A/R class (a full msr_mask).
def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary, def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
"mrs", "\t$Rd, $mask", []>, "mrs", "\t$Rd, $mask", []>,
Requires<[IsThumb2,IsMClass]> { Requires<[IsThumb,IsMClass]> {
bits<4> Rd; bits<4> Rd;
bits<8> mask; bits<8> mask;
let Inst{31-12} = 0b11110011111011111000; let Inst{31-12} = 0b11110011111011111000;
@ -3682,7 +3682,7 @@ def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
// Move from ARM core register to Special Register // Move from ARM core register to Special Register
def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
NoItinerary, "msr", "\t$SYSm, $Rn", []>, NoItinerary, "msr", "\t$SYSm, $Rn", []>,
Requires<[IsThumb2,IsMClass]> { Requires<[IsThumb,IsMClass]> {
bits<8> SYSm; bits<8> SYSm;
bits<4> Rn; bits<4> Rn;
let Inst{31-21} = 0b11110011100; let Inst{31-21} = 0b11110011100;
@ -4002,9 +4002,9 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
// Memory barriers // Memory barriers
def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>; def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>; def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>; def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
// width specifier. // width specifier.

32
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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@ -51,23 +51,32 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
Idx = 6; Idx = 6;
} }
bool NoCPU = CPU == "generic" || CPU.empty();
std::string ARMArchFeature; std::string ARMArchFeature;
if (Idx) { if (Idx) {
unsigned SubVer = TT[Idx]; unsigned SubVer = TT[Idx];
if (SubVer >= '7' && SubVer <= '9') { if (SubVer >= '7' && SubVer <= '9') {
if (Len >= Idx+2 && TT[Idx+1] == 'm') { if (Len >= Idx+2 && TT[Idx+1] == 'm') {
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass if (NoCPU)
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass"; // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, if (NoCPU)
// FeatureT2XtPk, FeatureMClass // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass"; // FeatureT2XtPk, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
} else { } else {
// v7 CPUs have lots of different feature sets. If no CPU is specified, // v7 CPUs have lots of different feature sets. If no CPU is specified,
// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
// the "minimum" feature set and use CPU string to figure out the exact // the "minimum" feature set and use CPU string to figure out the exact
// features. // features.
if (CPU == "generic") if (NoCPU)
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk"; ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
else else
@ -77,10 +86,13 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
} else if (SubVer == '6') { } else if (SubVer == '6') {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
ARMArchFeature = "+v6t2"; ARMArchFeature = "+v6t2";
else if (Len >= Idx+2 && TT[Idx+1] == 'm') else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
// v6m: FeatureNoARM, FeatureMClass if (NoCPU)
ARMArchFeature = "+v6t2,+noarm,+mclass"; // v6m: FeatureNoARM, FeatureMClass
else ARMArchFeature = "+v6,+noarm,+mclass";
else
ARMArchFeature = "+v6";
} else
ARMArchFeature = "+v6"; ARMArchFeature = "+v6";
} else if (SubVer == '5') { } else if (SubVer == '5') {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')

12
test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
; rdar://11331541
define i32 @t(i32 %a) nounwind {
; CHECK: t:
; CHECK: asrs r1, r0, #31
; CHECK: eors r1, r0
%tmp0 = ashr i32 %a, 31
%tmp1 = xor i32 %tmp0, %a
ret i32 %tmp1
}