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- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3017,7 +3017,7 @@ def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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"isb", "\t$opt",
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"isb", "\t$opt",
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[]>, Requires<[IsThumb2, HasDB]> {
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[]>, Requires<[IsThumb, HasDB]> {
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bits<4> opt;
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bits<4> opt;
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let Inst{31-4} = 0xf3bf8f6;
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let Inst{31-4} = 0xf3bf8f6;
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let Inst{3-0} = opt;
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let Inst{3-0} = opt;
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@ -3646,7 +3646,7 @@ def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
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// the A/R class (a full msr_mask).
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// the A/R class (a full msr_mask).
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def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
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def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
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"mrs", "\t$Rd, $mask", []>,
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"mrs", "\t$Rd, $mask", []>,
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Requires<[IsThumb2,IsMClass]> {
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Requires<[IsThumb,IsMClass]> {
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bits<4> Rd;
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bits<4> Rd;
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bits<8> mask;
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bits<8> mask;
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let Inst{31-12} = 0b11110011111011111000;
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let Inst{31-12} = 0b11110011111011111000;
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@ -3682,7 +3682,7 @@ def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
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// Move from ARM core register to Special Register
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// Move from ARM core register to Special Register
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def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
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def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
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NoItinerary, "msr", "\t$SYSm, $Rn", []>,
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NoItinerary, "msr", "\t$SYSm, $Rn", []>,
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Requires<[IsThumb2,IsMClass]> {
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Requires<[IsThumb,IsMClass]> {
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bits<8> SYSm;
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bits<8> SYSm;
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bits<4> Rn;
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bits<4> Rn;
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let Inst{31-21} = 0b11110011100;
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let Inst{31-21} = 0b11110011100;
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@ -4002,9 +4002,9 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
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(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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// Memory barriers
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// Memory barriers
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def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
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def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
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def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
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def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
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def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
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def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
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// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
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// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
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// width specifier.
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// width specifier.
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@ -51,23 +51,32 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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Idx = 6;
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Idx = 6;
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}
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}
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bool NoCPU = CPU == "generic" || CPU.empty();
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std::string ARMArchFeature;
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std::string ARMArchFeature;
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if (Idx) {
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if (Idx) {
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unsigned SubVer = TT[Idx];
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unsigned SubVer = TT[Idx];
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if (SubVer >= '7' && SubVer <= '9') {
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if (SubVer >= '7' && SubVer <= '9') {
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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if (NoCPU)
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
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} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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if (NoCPU)
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// FeatureT2XtPk, FeatureMClass
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else {
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} else {
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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// features.
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if (CPU == "generic")
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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else
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@ -77,10 +86,13 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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} else if (SubVer == '6') {
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} else if (SubVer == '6') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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ARMArchFeature = "+v6t2";
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ARMArchFeature = "+v6t2";
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else if (Len >= Idx+2 && TT[Idx+1] == 'm')
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else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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// v6m: FeatureNoARM, FeatureMClass
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if (NoCPU)
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ARMArchFeature = "+v6t2,+noarm,+mclass";
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// v6m: FeatureNoARM, FeatureMClass
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else
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ARMArchFeature = "+v6,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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} else
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ARMArchFeature = "+v6";
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ARMArchFeature = "+v6";
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} else if (SubVer == '5') {
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} else if (SubVer == '5') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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12
test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
Normal file
12
test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
Normal file
@ -0,0 +1,12 @@
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; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
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; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
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; rdar://11331541
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define i32 @t(i32 %a) nounwind {
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; CHECK: t:
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; CHECK: asrs r1, r0, #31
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; CHECK: eors r1, r0
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%tmp0 = ashr i32 %a, 31
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%tmp1 = xor i32 %tmp0, %a
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ret i32 %tmp1
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}
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