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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
[mips] Instruction selection patterns for DSP-ASE vector shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -26,6 +26,8 @@ def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
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SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
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def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
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SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>]>;
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class MipsDSPBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof>;
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@ -74,6 +76,9 @@ def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
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def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
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def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
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def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
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def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
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// Flags.
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class UseAC {
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@ -348,6 +353,7 @@ class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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bit hasSideEffects = 1;
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}
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class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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@ -659,19 +665,19 @@ class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
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ClearDefs;
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// Shift
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class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
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class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
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NoItinerary, DSPRegs>;
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class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
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NoItinerary, DSPRegs>;
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class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
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class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
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class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
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NoItinerary, DSPRegs>;
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class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
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@ -683,7 +689,7 @@ class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
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class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
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NoItinerary, DSPRegs>;
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class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
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class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
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@ -1028,7 +1034,7 @@ class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
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CPURegs>, ClearDefs;
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// Shift
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class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
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class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
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@ -1041,7 +1047,7 @@ class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
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class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
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class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
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NoItinerary, DSPRegs>, ClearDefs;
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class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
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@ -1280,6 +1286,24 @@ def : DSPBinPat<ADDSC, i32, addc>;
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def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
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def : DSPBinPat<ADDWC, i32, adde>;
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// Shift immediate patterns.
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class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
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ImmLeaf Imm, Predicate Pred = HasDSP> :
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DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
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def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>;
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def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>;
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def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>;
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def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
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def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
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def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
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def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>;
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def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>;
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def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>;
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def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
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def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
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def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
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@ -197,6 +197,9 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
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case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
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case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
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case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
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case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
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case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
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default: return NULL;
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}
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}
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@ -143,6 +143,11 @@ namespace llvm {
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MSUB_DSP,
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MSUBU_DSP,
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// DSP shift nodes.
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SHLL_DSP,
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SHRA_DSP,
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SHRL_DSP,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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@ -52,6 +52,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::STORE, VecTys[i], Legal);
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setOperationAction(ISD::BITCAST, VecTys[i], Legal);
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}
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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}
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if (Subtarget->hasDSPR2())
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@ -314,6 +318,59 @@ static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
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SelectionDAG &DAG,
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const MipsSubtarget *Subtarget) {
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// See if this is a vector splat immediate node.
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
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BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
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if (!BV || !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
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HasAnyUndefs, EltSize,
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!Subtarget->isLittle()))
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return SDValue();
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return DAG.getNode(Opc, N->getDebugLoc(), Ty, N->getOperand(0),
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DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
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}
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static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
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}
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static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
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}
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static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
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}
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SDValue
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MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -323,6 +380,12 @@ MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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return performADDECombine(N, DAG, DCI, Subtarget);
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case ISD::SUBE:
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return performSUBECombine(N, DAG, DCI, Subtarget);
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case ISD::SHL:
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return performSHLCombine(N, DAG, DCI, Subtarget);
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case ISD::SRA:
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return performSRACombine(N, DAG, DCI, Subtarget);
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case ISD::SRL:
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return performSRLCombine(N, DAG, DCI, Subtarget);
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default:
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return MipsTargetLowering::PerformDAGCombine(N, DCI);
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}
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@ -128,3 +128,78 @@ entry:
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ret i64 %add
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}
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; R1: shift1_v2i16_shl_:
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; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shl = shl <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: shift1_v2i16_sra_:
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; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shr = ashr <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: shift1_v2ui16_srl_:
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; R1-NOT: shrl.ph
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; R2: shift1_v2ui16_srl_:
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; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shr = lshr <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: shift1_v4i8_shl_:
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; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shl = shl <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: shift1_v4i8_sra_:
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; R1-NOT: shra.qb
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; R2: shift1_v4i8_sra_:
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; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shr = ashr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: shift1_v4ui8_srl_:
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; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shr = lshr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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