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Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
PR10955 and PR10948. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
f2d15db05b
commit
97dc60b759
@ -1973,73 +1973,44 @@ def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
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// sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
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multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
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SDNode OpNode, ValueType VT, PatFrag ld_frag,
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string asm, string asm_alt> {
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let isAsmParserOnly = 1 in {
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def rr : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
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asm, []>;
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let mayLoad = 1 in
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def rm : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
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asm, []>;
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}
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def rr : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
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[(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
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def rm : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
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[(set RC:$dst, (OpNode (VT RC:$src1),
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(ld_frag addr:$src2), imm:$cc))]>;
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// Accept explicit immediate argument form instead of comparison code.
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def rr_alt : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
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asm_alt, []>;
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let mayLoad = 1 in
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def rm_alt : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
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asm_alt, []>;
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let neverHasSideEffects = 1 in {
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def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
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let mayLoad = 1 in
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def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
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}
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}
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let neverHasSideEffects = 1 in {
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defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
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"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XS, VEX_4V;
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defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
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"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XD, VEX_4V;
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}
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defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
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"cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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XS, VEX_4V;
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defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
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"cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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XD, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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def CMPSSrr : SIi8<0xC2, MRMSrcReg,
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(outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
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"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2,
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imm:$cc))]>, XS;
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def CMPSSrm : SIi8<0xC2, MRMSrcMem,
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(outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
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"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (X86cmpss (f32 FR32:$src1),
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(loadf32 addr:$src2), imm:$cc))]>, XS;
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def CMPSDrr : SIi8<0xC2, MRMSrcReg,
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(outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
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"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2,
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imm:$cc))]>, XD;
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def CMPSDrm : SIi8<0xC2, MRMSrcMem,
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(outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
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"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2),
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imm:$cc))]>, XD;
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}
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let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
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def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
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(outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
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"cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
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def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
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(outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
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"cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
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def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
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(outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
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"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
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def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
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(outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
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"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
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defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
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"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
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"cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
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XS;
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defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
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"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
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"cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
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XD;
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}
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multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
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@ -130,3 +130,21 @@ define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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ret <32 x i8> %x
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}
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;; Scalar comparison
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; CHECK: scalarcmpA
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; CHECK: vcmpeqsd
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define i32 @scalarcmpA() uwtable ssp {
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%cmp29 = fcmp oeq double undef, 0.000000e+00
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%res = zext i1 %cmp29 to i32
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ret i32 %res
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}
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; CHECK: scalarcmpB
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; CHECK: vcmpeqss
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define i32 @scalarcmpB() uwtable ssp {
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%cmp29 = fcmp oeq float undef, 0.000000e+00
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%res = zext i1 %cmp29 to i32
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ret i32 %res
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}
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