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Fix handling of ARM negative pc-relative fixups for loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -131,8 +131,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default: llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4: return 4;
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case ARM::fixup_arm_pcrel_12: return 2;
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case ARM::fixup_arm_vfp_pcrel_12: return 1;
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case ARM::fixup_arm_pcrel_12: return 3;
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case ARM::fixup_arm_vfp_pcrel_12: return 3;
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case ARM::fixup_arm_branch: return 3;
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}
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}
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@ -143,14 +143,36 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4:
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return Value;
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case ARM::fixup_arm_pcrel_12:
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case ARM::fixup_arm_pcrel_12: {
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bool isAdd = true;
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// ARM PC-relative values are offset by 8.
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return Value - 8;
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Value -= 8;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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assert ((Value < 4096) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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return Value;
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}
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case ARM::fixup_arm_branch:
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case ARM::fixup_arm_vfp_pcrel_12:
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// These values don't encode the low two bits since they're always zero.
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// Offset by 8 just as above.
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return (Value - 8) >> 2;
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case ARM::fixup_arm_vfp_pcrel_12: {
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// Offset by 8 just as above.
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Value = Value - 8;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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// These values don't encode the low two bits since they're always zero.
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Value >>= 2;
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assert ((Value < 256) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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return Value;
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}
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}
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}
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@ -46,8 +46,8 @@ public:
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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// name offset bits flags
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{ "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_vfp_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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};
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@ -395,6 +395,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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if (!MO.isReg()) {
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Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
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Imm12 = 0;
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isAdd = false ; // 'U' bit is set as part of the fixup.
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assert(MO.isExpr() && "Unexpected machine operand type!");
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const MCExpr *Expr = MO.getExpr();
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@ -574,11 +575,13 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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// {8} = (U)nsigned (add == '1', sub == '0')
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// {7-0} = imm8
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unsigned Reg, Imm8;
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bool isAdd;
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// If The first operand isn't a register, we have a label reference.
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (!MO.isReg()) {
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Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
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Imm8 = 0;
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isAdd = false; // 'U' bit is handled as part of the fixup.
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assert(MO.isExpr() && "Unexpected machine operand type!");
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const MCExpr *Expr = MO.getExpr();
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@ -586,12 +589,14 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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++MCNumCPRelocations;
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} else
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} else {
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EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
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isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
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}
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uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
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// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
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if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
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if (isAdd)
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Binary |= (1 << 8);
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Binary |= (Reg << 9);
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return Binary;
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