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support bsr, and more .td simplification

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22543 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
2005-07-28 18:14:47 +00:00
parent fe660397e1
commit 98169be50b
6 changed files with 76 additions and 48 deletions
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lib/Target/Alpha/AlphaCodeEmitter.cpp
+3
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@@ -180,6 +180,9 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
int Offset = 0;
bool useGOT = false;
switch (MI.getOpcode()) {
case Alpha::BSR:
Reloc = Alpha::reloc_bsr;
break;
case Alpha::LDLr:
case Alpha::LDQr:
case Alpha::LDBUr: