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Make 91378 more conservative.

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1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91399 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-12-15 03:00:32 +00:00
parent bc8858c3b0
commit 9818c043d2
2 changed files with 11 additions and 14 deletions
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12
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3291,10 +3291,20 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if (SCC.getNode()) return SCC;
}
// (zext (shl (zext x), y)) -> (shl (zext x), (zext y))
// (zext (shl (zext x), cst)) -> (shl (zext x), cst)
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
isa<ConstantSDNode>(N0.getOperand(1)) &&
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
N0.hasOneUse()) {
if (N0.getOpcode() == ISD::SHL) {
// If the original shl may be shifting out bits, do not perform this
// transformation.
unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
if (ShAmt > KnownZeroBits)
return SDValue();
}
DebugLoc dl = N->getDebugLoc();
return DAG.getNode(N0.getOpcode(), dl, VT,
DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),

13
test/CodeGen/X86/zext-shl.ll
View File

@ -23,16 +23,3 @@ entry:
%2 = zext i16 %1 to i32
ret i32 %2
}
define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp {
entry:
; CHECK: t3:
; CHECK: shll
; CHECK-NOT: movzwl
; CHECK: ret
%0 = zext i8 %x to i16
%1 = zext i8 %y to i16
%2 = shl i16 %0, %1
%3 = zext i16 %2 to i32
ret i32 %3
}