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AArch64: Avoid shifts by 64, that's undefined behavior.

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No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175400 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-02-17 17:55:32 +00:00
parent 906727dcfe
commit 9831bf06e8
1 changed files with 3 additions and 3 deletions
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6
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2512,7 +2512,7 @@ static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
N = N.getOperand(0);
} else {
// Mask is the whole width.
Mask = (1ULL << N.getValueType().getSizeInBits()) - 1;
Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
}
if (N.getOpcode() == AArch64ISD::BFI) {
@ -2590,7 +2590,7 @@ static SDValue tryCombineToBFI(SDNode *N,
DAG.getConstant(Width, MVT::i64));
// Mask is trivial
if ((LHSMask | RHSMask) == (1ULL << VT.getSizeInBits()) - 1)
if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
return BFI;
return DAG.getNode(ISD::AND, DL, VT, BFI,
@ -2660,7 +2660,7 @@ static SDValue tryCombineToLargerBFI(SDNode *N,
BFI.getOperand(2), BFI.getOperand(3));
// If the masking is trivial, we don't need to create it.
if ((ExtraMask | ExistingMask) == (1ULL << VT.getSizeInBits()) - 1)
if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
return BFI;
return DAG.getNode(ISD::AND, DL, VT, BFI,