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ARM parsing aliases for VLD1 single register all lanes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-11-30 01:09:44 +00:00
parent 3d925d24e8
commit 98b05a57b6
6 changed files with 142 additions and 6 deletions
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7
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@@ -1029,3 +1029,10 @@ void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
}
void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
}