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Make LowerSubregs' debug output for EXTRACT_SUBREG consistent with

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that of INSERT_SUBREG and SUBREG_TO_REG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61218 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-18 22:11:34 +00:00
parent f04865f234
commit 98c206921a
1 changed files with 6 additions and 1 deletions
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7
lib/CodeGen/LowerSubregs.cpp
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@ -80,7 +80,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
DOUT << "subreg: CONVERTING: " << *MI; DOUT << "subreg: CONVERTING: " << *MI;
if (SrcReg != DstReg) { if (SrcReg == DstReg) {
// No need to insert an identify copy instruction.
DOUT << "subreg: eliminated!";
} else {
// Insert copy
const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg); const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) && assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
"Extract subreg and Dst must be of same register class"); "Extract subreg and Dst must be of same register class");
@ -177,6 +181,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
#ifndef NDEBUG #ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI; MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI); DOUT << "subreg: " << *(--dMI);