mirror of
https://github.com/c64scene-ar/llvm-6502.git
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R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
a92f8ee2f3
commit
98ce62780e
@ -469,6 +469,9 @@ static bool
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isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
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const std::vector<std::pair<int, unsigned> > &TransOps,
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unsigned ConstCount) {
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// TransALU can't read 3 constants
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if (ConstCount > 2)
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return false;
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for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
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const std::pair<int, unsigned> &Src = TransOps[i];
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unsigned Cycle = getTransSwizzle(TransSwz, i);
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@ -9,7 +9,6 @@
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//
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/// \file
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/// \brief R600 Machine Scheduler interface
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// TODO: Scheduling is optimised for VLIW4 arch, modify it to support TRANS slot
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//
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//===----------------------------------------------------------------------===//
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@ -29,6 +28,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
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DAG = dag;
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TII = static_cast<const R600InstrInfo*>(DAG->TII);
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TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
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MRI = &DAG->MRI;
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CurInstKind = IDOther;
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CurEmitted = 0;
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@ -342,14 +342,16 @@ int R600SchedStrategy::getInstKind(SUnit* SU) {
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}
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}
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SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q) {
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SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
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if (Q.empty())
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return NULL;
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for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend();
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It != E; ++It) {
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SUnit *SU = *It;
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InstructionsGroupCandidate.push_back(SU->getInstr());
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if (TII->fitsConstReadLimitations(InstructionsGroupCandidate)) {
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if (TII->fitsConstReadLimitations(InstructionsGroupCandidate)
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&& (!AnyALU || !TII->isVectorOnly(SU->getInstr()))
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) {
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InstructionsGroupCandidate.pop_back();
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Q.erase((It + 1).base());
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return SU;
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@ -373,6 +375,8 @@ void R600SchedStrategy::PrepareNextSlot() {
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DEBUG(dbgs() << "New Slot\n");
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assert (OccupedSlotsMask && "Slot wasn't filled");
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OccupedSlotsMask = 0;
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// if (HwGen == AMDGPUSubtarget::NORTHERN_ISLANDS)
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// OccupedSlotsMask |= 16;
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InstructionsGroupCandidate.clear();
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LoadAlu();
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}
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@ -409,12 +413,12 @@ void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
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}
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}
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SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot) {
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SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) {
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static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
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SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]]);
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SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu);
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if (SlotedSU)
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return SlotedSU;
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SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny]);
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SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu);
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if (UnslotedSU)
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AssignSlot(UnslotedSU->getInstr(), Slot);
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return UnslotedSU;
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@ -434,30 +438,35 @@ SUnit* R600SchedStrategy::pickAlu() {
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// Bottom up scheduling : predX must comes first
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if (!AvailableAlus[AluPredX].empty()) {
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OccupedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluPredX]);
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return PopInst(AvailableAlus[AluPredX], false);
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}
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// Flush physical reg copies (RA will discard them)
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if (!AvailableAlus[AluDiscarded].empty()) {
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OccupedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluDiscarded]);
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return PopInst(AvailableAlus[AluDiscarded], false);
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}
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// If there is a T_XYZW alu available, use it
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if (!AvailableAlus[AluT_XYZW].empty()) {
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OccupedSlotsMask |= 15;
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return PopInst(AvailableAlus[AluT_XYZW]);
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return PopInst(AvailableAlus[AluT_XYZW], false);
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}
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}
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bool TransSlotOccuped = OccupedSlotsMask & 16;
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if (!TransSlotOccuped) {
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if (!TransSlotOccuped && VLIW5) {
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if (!AvailableAlus[AluTrans].empty()) {
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OccupedSlotsMask |= 16;
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return PopInst(AvailableAlus[AluTrans]);
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return PopInst(AvailableAlus[AluTrans], false);
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}
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SUnit *SU = AttemptFillSlot(3, true);
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if (SU) {
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OccupedSlotsMask |= 16;
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return SU;
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}
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}
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for (int Chan = 3; Chan > -1; --Chan) {
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bool isOccupied = OccupedSlotsMask & (1 << Chan);
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if (!isOccupied) {
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SUnit *SU = AttemptFillSlot(Chan);
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SUnit *SU = AttemptFillSlot(Chan, false);
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if (SU) {
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OccupedSlotsMask |= (1 << Chan);
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InstructionsGroupCandidate.push_back(SU->getInstr());
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@ -84,15 +84,16 @@ public:
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private:
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std::vector<MachineInstr *> InstructionsGroupCandidate;
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bool VLIW5;
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int getInstKind(SUnit *SU);
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bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
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AluKind getAluKind(SUnit *SU) const;
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void LoadAlu();
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unsigned AvailablesAluCount() const;
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SUnit *AttemptFillSlot (unsigned Slot);
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SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
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void PrepareNextSlot();
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SUnit *PopInst(std::vector<SUnit*> &Q);
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SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
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void AssignSlot(MachineInstr *MI, unsigned Slot);
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SUnit* pickAlu();
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@ -58,6 +58,8 @@ class R600PacketizerList : public VLIWPacketizerList {
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private:
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const R600InstrInfo *TII;
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const R600RegisterInfo &TRI;
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bool VLIW5;
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bool ConsideredInstUsesAlreadyWrittenVectorElement;
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unsigned getSlot(const MachineInstr *MI) const {
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return TRI.getHWRegChan(MI->getOperand(0).getReg());
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@ -74,7 +76,13 @@ private:
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MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
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if (I->isBundle())
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BI++;
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int LastDstChan = -1;
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do {
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bool isTrans = false;
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int BISlot = getSlot(BI);
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if (LastDstChan >= BISlot)
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isTrans = true;
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LastDstChan = BISlot;
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if (TII->isPredicated(BI))
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continue;
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int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
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@ -85,7 +93,7 @@ private:
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continue;
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}
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unsigned Dst = BI->getOperand(DstIdx).getReg();
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if (TII->isTransOnly(BI)) {
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if (isTrans || TII->isTransOnly(BI)) {
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Result[Dst] = AMDGPU::PS;
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continue;
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}
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@ -142,10 +150,14 @@ public:
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MachineDominatorTree &MDT)
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: VLIWPacketizerList(MF, MLI, MDT, true),
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TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
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TRI(TII->getRegisterInfo()) { }
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TRI(TII->getRegisterInfo()) {
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VLIW5 = !MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
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}
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// initPacketizerState - initialize some internal flags.
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void initPacketizerState() { }
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void initPacketizerState() {
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ConsideredInstUsesAlreadyWrittenVectorElement = false;
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}
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
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@ -172,8 +184,8 @@ public:
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// together.
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bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
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if (getSlot(MII) <= getSlot(MIJ) && !TII->isTransOnly(MII))
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return false;
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if (getSlot(MII) == getSlot(MIJ))
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ConsideredInstUsesAlreadyWrittenVectorElement = true;
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// Does MII and MIJ share the same pred_sel ?
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int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
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OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
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@ -211,6 +223,20 @@ public:
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std::vector<R600InstrInfo::BankSwizzle> &BS,
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bool &isTransSlot) {
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isTransSlot = TII->isTransOnly(MI);
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assert (!isTransSlot || VLIW5);
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// Is the dst reg sequence legal ?
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if (!isTransSlot && !CurrentPacketMIs.empty()) {
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if (getSlot(MI) <= getSlot(CurrentPacketMIs.back())) {
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if (ConsideredInstUsesAlreadyWrittenVectorElement &&
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!TII->isVectorOnly(MI) && VLIW5) {
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isTransSlot = true;
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DEBUG(dbgs() << "Considering as Trans Inst :"; MI->dump(););
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}
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else
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return false;
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}
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}
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// Are the Constants limitations met ?
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CurrentPacketMIs.push_back(MI);
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@ -278,6 +304,8 @@ public:
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return It;
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}
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endPacket(MI->getParent(), MI);
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if (TII->isTransOnly(MI))
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return MI;
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return VLIWPacketizerList::addToPacket(MI);
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}
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};
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@ -21,7 +21,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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;EG-CHECK: @test4
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;EG-CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: @test4
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@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fadd_v4f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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@ -2,7 +2,7 @@
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;Not checking arguments 2 and 3 to CNDE, because they may change between
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;registers and literal.x depending on what the optimizer does.
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;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
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entry:
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @fcmp_sext
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; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
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entry:
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@ -1,13 +1,13 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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;CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
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entry:
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@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fmul_v4f32
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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@ -2,7 +2,7 @@
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;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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@ -12,7 +12,7 @@ entry:
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; CHECK: @fneg_v4
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; CHECK: -PV
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; CHECK: -PV
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; CHECK: -T
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; CHECK: -PV
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; CHECK: -PV
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define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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@ -2,9 +2,9 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @fp_to_sint_v4i32
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; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI-CHECK: @fp_to_sint_v4i32
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; SI-CHECK: V_CVT_I32_F32_e32
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@ -2,7 +2,7 @@
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; CHECK: @fp_to_uint_v4i32
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; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW]}}
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; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fsub_v4f32
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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@ -3,7 +3,7 @@
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;Test that a select with reversed True/False values is correctly lowered
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;to a SETNE_INT. There should only be one SETNE_INT instruction.
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;CHECK: SETNE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;CHECK-NOT: SETNE_INT
|
||||
|
||||
define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
|
||||
|
||||
; CHECK: @main1
|
||||
; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}}
|
||||
; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}
|
||||
define void @main1() {
|
||||
main_body:
|
||||
%0 = load <4 x float> addrspace(8)* null
|
||||
|
||||
@ -7,7 +7,8 @@
|
||||
; ADD_INT literal.x KC0[2].Z, 5
|
||||
|
||||
; CHECK: @i32_literal
|
||||
; CHECK: ADD_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK: ADD_INT T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5
|
||||
define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
@ -23,7 +24,8 @@ entry:
|
||||
; ADD literal.x KC0[2].Z, 5.0
|
||||
|
||||
; CHECK: @float_literal
|
||||
; CHECK: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK: ADD T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.0
|
||||
define void @float_literal(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
|
||||
|
||||
; R600-CHECK: @amdgpu_trunc
|
||||
; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; SI-CHECK: @amdgpu_trunc
|
||||
; SI-CHECK: V_TRUNC_F32
|
||||
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
; CHECK-NEXT: .long 8
|
||||
|
||||
; Make sure the lds writes are using different addresses.
|
||||
; CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
|
||||
; CHECK: LDS_WRITE {{\** *}}{{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
|
||||
; CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]]
|
||||
|
||||
; GROUP_BARRIER must be the last instruction in a clause
|
||||
|
||||
@ -19,7 +19,8 @@ entry:
|
||||
; R600-CHECK: @rotl
|
||||
; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
|
||||
; R600-CHECK-NEXT: 32
|
||||
; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
|
||||
; R600-CHECK: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
|
||||
|
||||
|
||||
; SI-CHECK: @rotl
|
||||
; SI-CHECK: V_SUB_I32_e64 [[DST:VGPR[0-9]+]], 32, {{[SV]GPR[0-9]+}}
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
|
||||
|
||||
;CHECK-NOT: SETE
|
||||
;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,
|
||||
;CHECK-NEXT: {{[-0-9]+\(2.0}}
|
||||
;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,
|
||||
;CHECK: 1073741824
|
||||
define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
%1 = load float addrspace(1)* %in
|
||||
%2 = fcmp oeq float %1, 0.0
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
|
||||
|
||||
;CHECK-NOT: SETE_INT
|
||||
;CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,
|
||||
;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,
|
||||
;CHECK-NEXT: 2
|
||||
define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
%1 = load i32 addrspace(1)* %in
|
||||
|
||||
@ -5,7 +5,8 @@
|
||||
; SET*DX10 instructions.
|
||||
|
||||
; CHECK: @fcmp_une_select_fptosi
|
||||
; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -18,7 +19,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_une_select_i32
|
||||
; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -29,7 +31,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ueq_select_fptosi
|
||||
; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -42,7 +45,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ueq_select_i32
|
||||
; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -53,7 +57,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ugt_select_fptosi
|
||||
; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -66,7 +71,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ugt_select_i32
|
||||
; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -77,7 +83,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_uge_select_fptosi
|
||||
; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -90,7 +97,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_uge_select_i32
|
||||
; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -101,7 +109,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ule_select_fptosi
|
||||
; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -114,7 +123,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ule_select_i32
|
||||
; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -125,7 +135,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ult_select_fptosi
|
||||
; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -138,7 +149,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ult_select_i32
|
||||
; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
|
||||
|
||||
;EG-CHECK: @test2
|
||||
;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI-CHECK: @test2
|
||||
;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
|
||||
@ -19,10 +19,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
}
|
||||
|
||||
;EG-CHECK: @test4
|
||||
;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI-CHECK: @test4
|
||||
;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
|
||||
|
||||
@ -3,7 +3,8 @@
|
||||
; These tests are for condition codes that are not supported by the hardware
|
||||
|
||||
; CHECK: @slt
|
||||
; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5(7.006492e-45)
|
||||
define void @slt(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
@ -14,7 +15,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @ult_i32
|
||||
; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5(7.006492e-45)
|
||||
define void @ult_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
@ -25,7 +27,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @ult_float
|
||||
; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @ult_float(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -36,7 +39,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @olt
|
||||
; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
;CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @olt(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -47,7 +51,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @sle
|
||||
; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 6(8.407791e-45)
|
||||
define void @sle(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
@ -58,7 +63,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @ule_i32
|
||||
; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 6(8.407791e-45)
|
||||
define void @ule_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
@ -69,7 +75,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @ule_float
|
||||
; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGE {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @ule_float(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
@ -80,7 +87,8 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @ole
|
||||
; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK: SETGE {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT:1084227584(5.000000e+00)
|
||||
define void @ole(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
|
||||
|
||||
;EG-CHECK: @test_select_v2i32
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI-CHECK: @test_select_v2i32
|
||||
;SI-CHECK: V_CNDMASK_B32_e64
|
||||
@ -20,8 +20,8 @@ entry:
|
||||
}
|
||||
|
||||
;EG-CHECK: @test_select_v2f32
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI-CHECK: @test_select_v2f32
|
||||
;SI-CHECK: V_CNDMASK_B32_e64
|
||||
@ -38,10 +38,10 @@ entry:
|
||||
}
|
||||
|
||||
;EG-CHECK: @test_select_v4i32
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI-CHECK: @test_select_v4i32
|
||||
;SI-CHECK: V_CNDMASK_B32_e64
|
||||
@ -60,10 +60,10 @@ entry:
|
||||
}
|
||||
|
||||
;EG-CHECK: @test_select_v4f32
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
|
||||
entry:
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
; R600-CHECK: @ngroups_x
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[0].X
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].X
|
||||
; SI-CHECK: @ngroups_x
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -17,7 +17,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @ngroups_y
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[0].Y
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].Y
|
||||
; SI-CHECK: @ngroups_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -31,7 +31,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @ngroups_z
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[0].Z
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].Z
|
||||
; SI-CHECK: @ngroups_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -45,7 +45,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @global_size_x
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[0].W
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[0].W
|
||||
; SI-CHECK: @global_size_x
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -59,7 +59,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @global_size_y
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[1].X
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].X
|
||||
; SI-CHECK: @global_size_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -73,7 +73,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @global_size_z
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[1].Y
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].Y
|
||||
; SI-CHECK: @global_size_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -87,7 +87,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @local_size_x
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[1].Z
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].Z
|
||||
; SI-CHECK: @local_size_x
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -101,7 +101,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @local_size_y
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[1].W
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[1].W
|
||||
; SI-CHECK: @local_size_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
@ -115,7 +115,7 @@ entry:
|
||||
|
||||
; R600-CHECK: @local_size_z
|
||||
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV * [[VAL]], KC0[2].X
|
||||
; R600-CHECK: MOV {{\** *}}[[VAL]], KC0[2].X
|
||||
; SI-CHECK: @local_size_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
|
||||
|
||||
89
test/CodeGen/R600/wrong-transalu-pos-fix.ll
Normal file
89
test/CodeGen/R600/wrong-transalu-pos-fix.ll
Normal file
@ -0,0 +1,89 @@
|
||||
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
|
||||
|
||||
; We want all MULLO_INT inst to be last in their instruction group
|
||||
;CHECK: @fill3d
|
||||
;CHECK-NOT: MULLO_INT T[0-9]+
|
||||
|
||||
; ModuleID = 'radeon'
|
||||
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
|
||||
target triple = "r600--"
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @fill3d(i32 addrspace(1)* nocapture %out) #0 {
|
||||
entry:
|
||||
%x.i = tail call i32 @llvm.r600.read.global.size.x() #1
|
||||
%y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
|
||||
%mul = mul i32 %y.i18, %x.i
|
||||
%z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
|
||||
%mul3 = mul i32 %mul, %z.i17
|
||||
%x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
|
||||
%x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
|
||||
%mul26.i = mul i32 %x.i12.i, %x.i.i
|
||||
%x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
%add.i16 = add i32 %x.i4.i, %mul26.i
|
||||
%mul7 = mul i32 %add.i16, %y.i18
|
||||
%y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
|
||||
%y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
|
||||
%mul30.i = mul i32 %y.i14.i, %y.i.i
|
||||
%y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
|
||||
%add.i14 = add i32 %mul30.i, %mul7
|
||||
%mul819 = add i32 %add.i14, %y.i6.i
|
||||
%add = mul i32 %mul819, %z.i17
|
||||
%z.i.i = tail call i32 @llvm.r600.read.tgid.z() #1
|
||||
%z.i16.i = tail call i32 @llvm.r600.read.local.size.z() #1
|
||||
%mul33.i = mul i32 %z.i16.i, %z.i.i
|
||||
%z.i8.i = tail call i32 @llvm.r600.read.tidig.z() #1
|
||||
%add.i = add i32 %z.i8.i, %mul33.i
|
||||
%add13 = add i32 %add.i, %add
|
||||
%arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %add13
|
||||
store i32 %mul3, i32 addrspace(1)* %arrayidx, align 4, !tbaa !3
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.y() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tgid.z() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.local.size.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.local.size.y() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.local.size.z() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tidig.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tidig.y() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.tidig.z() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.global.size.x() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.global.size.y() #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.r600.read.global.size.z() #1
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
!opencl.kernels = !{!0, !1, !2}
|
||||
|
||||
!0 = metadata !{null}
|
||||
!1 = metadata !{null}
|
||||
!2 = metadata !{void (i32 addrspace(1)*)* @fill3d}
|
||||
!3 = metadata !{metadata !"int", metadata !4}
|
||||
!4 = metadata !{metadata !"omnipotent char", metadata !5}
|
||||
!5 = metadata !{metadata !"Simple C/C++ TBAA"}
|
||||
Loading…
Reference in New Issue
Block a user