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Add a few more altivec intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -131,7 +131,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty],
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Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty],
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[InstrNoMem]>;
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[InstrNoMem]>;
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// Saturating adds and subs.
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// Saturating adds, subs, and multiply-adds
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def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">,
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def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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[InstrNoMem]>;
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[InstrNoMem]>;
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@ -150,6 +150,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">,
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def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[InstrNoMem]>;
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[InstrNoMem]>;
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def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
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def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
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def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
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def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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@ -219,6 +225,20 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">,
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def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
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// Merges
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def int_ppc_altivec_vmrghh : GCCBuiltin<"__builtin_altivec_vmrghh">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[InstrNoMem]>;
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def int_ppc_altivec_vmrghw : GCCBuiltin<"__builtin_altivec_vmrghw">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[InstrNoMem]>;
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def int_ppc_altivec_vmrglh : GCCBuiltin<"__builtin_altivec_vmrglh">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[InstrNoMem]>;
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def int_ppc_altivec_vmrglw : GCCBuiltin<"__builtin_altivec_vmrglw">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[InstrNoMem]>;
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// Left Shifts.
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// Left Shifts.
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def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
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def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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@ -276,6 +296,9 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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[InstrNoMem]>;
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[InstrNoMem]>;
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// Miscellaneous.
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// Miscellaneous.
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def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty, llvm_v16i8_ty], [InstrNoMem]>;
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def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
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def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
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llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
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@ -300,8 +300,8 @@ bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) {
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if (OpVal.Val == 0) return false; // All UNDEF: use implicit def.
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if (OpVal.Val == 0) return false; // All UNDEF: use implicit def.
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unsigned ValSizeInBytes;
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unsigned ValSizeInBytes = 0;
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uint64_t Value;
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uint64_t Value = 0;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
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Value = CN->getValue();
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Value = CN->getValue();
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ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
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ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
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@ -121,7 +121,14 @@ def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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Requires<[FPContractions]>;
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def VMHADDSHS : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vmhaddshs $vD, $vA, $vB, $vC", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
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def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vmhraddshs $vD, $vA, $vB, $vC", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
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def VPERM : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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def VPERM : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vperm $vD, $vA, $vB, $vC", VecPerm,
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"vperm $vD, $vA, $vB, $vC", VecPerm,
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[(set VRRC:$vD,
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[(set VRRC:$vD,
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@ -213,6 +220,22 @@ def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vminfp $vD, $vA, $vB", VecFP,
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"vminfp $vD, $vA, $vB", VecFP,
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[]>;
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[]>;
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def VMRGHH : VXForm_1<76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmrghh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
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def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmrghh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
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def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmrglh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
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def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmrglh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
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def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
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def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
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"vrefp $vD, $vB", VecFP,
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"vrefp $vD, $vB", VecFP,
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[(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
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@ -598,7 +621,8 @@ def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
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(VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
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def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
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(v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
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(v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
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@ -54,13 +54,11 @@ lvsl/lvsr
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mf*
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mf*
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vavg*
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vavg*
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vmax*
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vmax*
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vmhaddshs/vmhraddshs
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vmin*
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vmin*
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vmladduhm
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vmladduhm
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vmr*
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vmr*
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vmsum*
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vmsum*
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vmul*
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vmul*
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vperm
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vpk*
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vpk*
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vsel (some aliases only accessible using builtins)
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vsel (some aliases only accessible using builtins)
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vup*
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vup*
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