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[mips] Change lwl and lwr in inlineasm_constraint.ll to lw

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Summary:
lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test
is to check that the '$1' expands to '0($x)' rather than to test something related
to the lwl or lwr instructions so we can simply switch to lw.

Depends on D3842

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-05-22 11:51:06 +00:00
parent 8afb08e5b5
commit 98eba92334
1 changed files with 3 additions and 3 deletions
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6
test/CodeGen/Mips/inlineasm_constraint.ll
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@ -54,10 +54,10 @@ entry:
; Now R Which takes the address of c
%c = alloca i32, align 4
store i32 -4469539, i32* %c, align 4
%8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1
%8 = call i32 asm sideeffect "lw $0, 1 + $1\0A\09lw $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1
; CHECK: #APP
; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}})
; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}})
; CHECK: lw ${{[0-9]+}}, 1 + 0(${{[0-9]+}})
; CHECK: lw ${{[0-9]+}}, 2 + 0(${{[0-9]+}})
; CHECK: #NO_APP
ret i32 0