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[mips][FastISel] Handle calls with non legal types i8 and i16.
Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
parent
d8b1e16033
commit
98ed1175d9
@ -1000,7 +1000,9 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
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}
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}
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}
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if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
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if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
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(ArgVT == MVT::i8)) &&
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VA.isMemLoc()) {
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switch (VA.getLocMemOffset()) {
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case 0:
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VA.convertToReg(Mips::A0);
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@ -5,6 +5,36 @@
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; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
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declare void @xb(i8)
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define void @cxb() {
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; ALL-LABEL: cxb:
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; ALL: addiu $[[T0:[0-9]+]], $zero, 10
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; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
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; 32R1: sra $4, $[[T1]], 24
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; 32R2: seb $4, $[[T0]]
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call void @xb(i8 10)
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ret void
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}
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declare void @xh(i16)
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define void @cxh() {
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; ALL-LABEL: cxh:
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; ALL: addiu $[[T0:[0-9]+]], $zero, 10
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; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
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; 32R1: sra $4, $[[T1]], 16
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; 32R2: seh $4, $[[T0]]
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call void @xh(i16 10)
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ret void
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}
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declare void @xi(i32)
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define void @cxi() {
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@ -17,6 +47,44 @@ define void @cxi() {
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ret void
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}
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declare void @xbb(i8, i8)
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define void @cxbb() {
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; ALL-LABEL: cxbb:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
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; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
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; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
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; 32R2-DAG: seb $4, $[[T0]]
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; 32R2-DAG: seb $5, $[[T1]]
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call void @xbb(i8 76, i8 101)
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ret void
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}
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declare void @xhh(i16, i16)
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define void @cxhh() {
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; ALL-LABEL: cxhh:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
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; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
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; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
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; 32R2-DAG: seh $4, $[[T0]]
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; 32R2-DAG: seh $5, $[[T1]]
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call void @xhh(i16 76, i16 101)
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ret void
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}
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declare void @xii(i32, i32)
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define void @cxii() {
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@ -30,6 +98,52 @@ define void @cxii() {
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ret void
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}
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declare void @xccc(i8, i8, i8)
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define void @cxccc() {
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; ALL-LABEL: cxccc:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
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; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
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; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24
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; 32R1-DAG: sra $4, $[[T3]], 24
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
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; 32R1-DAG: sra $5, $[[T4]], 24
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; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24
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; 32R1-DAG: sra $6, $[[T5]], 24
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; 32R2-DAG: seb $4, $[[T0]]
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; 32R2-DAG: seb $5, $[[T1]]
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; 32R2-DAG: seb $6, $[[T2]]
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call void @xccc(i8 88, i8 44, i8 11)
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ret void
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}
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declare void @xhhh(i16, i16, i16)
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define void @cxhhh() {
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; ALL-LABEL: cxhhh:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
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; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
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; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16
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; 32R1-DAG: sra $4, $[[T3]], 16
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
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; 32R1-DAG: sra $5, $[[T4]], 16
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; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
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; 32R1-DAG: sra $6, $[[T5]], 16
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; 32R2-DAG: seh $4, $[[T0]]
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; 32R2-DAG: seh $5, $[[T1]]
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; 32R2-DAG: seh $6, $[[T2]]
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call void @xhhh(i16 88, i16 44, i16 11)
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ret void
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}
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declare void @xiii(i32, i32, i32)
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define void @cxiii() {
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@ -44,6 +158,76 @@ define void @cxiii() {
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ret void
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}
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declare void @xcccc(i8, i8, i8, i8)
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define void @cxcccc() {
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; ALL-LABEL: cxcccc:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
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; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
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; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
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; FIXME: We should avoid the unnecessary spill/reload here.
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
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; 32R1-DAG: sw $4, 16($sp)
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; 32R1-DAG: move $4, $[[T5]]
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; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24
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; 32R1-DAG: sra $5, $[[T6]], 24
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; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24
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; 32R1-DAG: sra $6, $[[T7]], 24
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; 32R1: lw $[[T8:[0-9]+]], 16($sp)
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; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24
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; 32R1: sra $7, $[[T9]], 24
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; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]
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; 32R2-DAG: sw $4, 16($sp)
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; 32R2-DAG: move $4, $[[T4]]
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; 32R2-DAG: seb $5, $[[T1]]
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; 32R2-DAG: seb $6, $[[T2]]
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; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
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; 32R2: seb $7, $[[T5]]
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call void @xcccc(i8 88, i8 44, i8 11, i8 33)
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ret void
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}
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declare void @xhhhh(i16, i16, i16, i16)
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define void @cxhhhh() {
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; ALL-LABEL: cxhhhh:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
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; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
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; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
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; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
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; FIXME: We should avoid the unnecessary spill/reload here.
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
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; 32R1-DAG: sw $4, 16($sp)
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; 32R1-DAG: move $4, $[[T5]]
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; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16
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; 32R1-DAG: sra $5, $[[T6]], 16
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; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16
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; 32R1-DAG: sra $6, $[[T7]], 16
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; 32R1: lw $[[T8:[0-9]+]], 16($sp)
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; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16
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; 32R1: sra $7, $[[T9]], 16
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; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]]
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; 32R2-DAG: sw $4, 16($sp)
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; 32R2-DAG: move $4, $[[T4]]
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; 32R2-DAG: seh $5, $[[T1]]
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; 32R2-DAG: seh $6, $[[T2]]
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; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
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; 32R2: seh $7, $[[T5]]
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call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
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ret void
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}
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declare void @xiiii(i32, i32, i32, i32)
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define void @cxiiii() {
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