mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
remove the patterns that I commented out in r98930, Dan verified
that they are dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d734919465
commit
99521af212
@ -2232,22 +2232,6 @@ def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
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def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(ADD64rm GR64:$src1, addr:$src2)>;
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/*
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// Memory-Register Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mr addr:$dst, GR64:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
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i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
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@ -2267,26 +2251,6 @@ def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
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(implicit EFLAGS)),
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(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
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/*
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// Memory-Register Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mr addr:$dst, GR64:$src2)>;
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// Memory-Integer Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
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i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
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i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Signed Integer Multiplication with EFLAGS result
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def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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@ -2316,45 +2280,18 @@ def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
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// INC and DEC with EFLAGS result. Note that these do not set CF.
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def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
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(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
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(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
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(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64_32m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
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(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
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*/
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def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
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(INC64r GR64:$src)>;
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/*
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def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64m addr:$dst)>;
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*/
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def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
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(DEC64r GR64:$src)>;
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/*
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def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64m addr:$dst)>;
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*/
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// Register-Register Logical Or with EFLAGS result
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def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
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@ -2374,22 +2311,6 @@ def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(OR64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical Or with EFLAGS result
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/*
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def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR64mr addr:$dst, GR64:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Logical XOr with EFLAGS result
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def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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@ -2408,23 +2329,6 @@ def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(XOR64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical XOr with EFLAGS result
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/*
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def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR64mr addr:$dst, GR64:$src2)>;
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def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
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i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Logical And with EFLAGS result
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def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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@ -2443,23 +2347,6 @@ def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(AND64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical And with EFLAGS result
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/*
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def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(AND64mr addr:$dst, GR64:$src2)>;
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def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(AND64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
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i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(AND64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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//===----------------------------------------------------------------------===//
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// X86-64 SSE Instructions
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//===----------------------------------------------------------------------===//
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@ -4785,44 +4785,6 @@ def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD8mr addr:$dst, GR8:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD16mr addr:$dst, GR16:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD32mr addr:$dst, GR32:$src2)>;
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// Memory-Integer Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD8mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD16mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD32mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
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def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
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(implicit EFLAGS)),
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@ -4862,44 +4824,6 @@ def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB8mr addr:$dst, GR8:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB16mr addr:$dst, GR16:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB32mr addr:$dst, GR32:$src2)>;
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// Memory-Integer Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB8mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB16mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB32mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
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def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register Signed Integer Multiply with EFLAGS result
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def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
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(implicit EFLAGS)),
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@ -4958,40 +4882,18 @@ def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
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// INC and DEC with EFLAGS result. Note that these do not set CF.
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def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
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(INC8r GR8:$src)>;
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/*
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def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC8m addr:$dst)>;
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*/
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def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
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(DEC8r GR8:$src)>;
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/*def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC8m addr:$dst)>;*/
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def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
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(INC16r GR16:$src)>, Requires<[In32BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC16m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
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(DEC16r GR16:$src)>, Requires<[In32BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC16m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
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(INC32r GR32:$src)>, Requires<[In32BitMode]>;
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/*def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC32m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
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(DEC32r GR32:$src)>, Requires<[In32BitMode]>;
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/*def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC32m addr:$dst)>, Requires<[In32BitMode]>;*/
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// Register-Register Or with EFLAGS result
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def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
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@ -5031,43 +4933,6 @@ def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
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def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Or with EFLAGS result
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def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR8mr addr:$dst, GR8:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR16mr addr:$dst, GR16:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR32mr addr:$dst, GR32:$src2)>;
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// Memory-Integer Or with EFLAGS result
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def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR8mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR16mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR32mi addr:$dst, imm:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR16mi8 addr:$dst, i16immSExt8:$src2)>;
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def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register XOr with EFLAGS result
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def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
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@ -5108,44 +4973,6 @@ def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register XOr with EFLAGS result
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def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR8mr addr:$dst, GR8:$src2)>;
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def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR16mr addr:$dst, GR16:$src2)>;
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def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR32mr addr:$dst, GR32:$src2)>;
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// Memory-Integer XOr with EFLAGS result
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def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
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addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(XOR8mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(XOR16mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(XOR32mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
|
||||
*/
|
||||
|
||||
// Register-Register And with EFLAGS result
|
||||
def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
@ -5185,44 +5012,6 @@ def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
||||
|
||||
/*
|
||||
// Memory-Register And with EFLAGS result
|
||||
def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND8mr addr:$dst, GR8:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND16mr addr:$dst, GR16:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND32mr addr:$dst, GR32:$src2)>;
|
||||
|
||||
// Memory-Integer And with EFLAGS result
|
||||
def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND8mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND16mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND32mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND16mi8 addr:$dst, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(AND32mi8 addr:$dst, i32immSExt8:$src2)>;
|
||||
*/
|
||||
|
||||
// -disable-16bit support.
|
||||
def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
|
||||
(MOV16mi addr:$dst, imm:$src)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user