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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Have SPU handle halfvec stores aligned by 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -470,6 +470,9 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
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setOperationAction(ISD::STORE, MVT::v2i32, Custom);
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setOperationAction(ISD::STORE, MVT::v2f32, Custom);
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setShiftAmountType(MVT::i32);
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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@ -518,6 +521,8 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
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node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
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node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
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node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
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node_names[(unsigned) SPUISD::HALF2VEC] = "SPUISD::HALF2VEC";
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node_names[(unsigned) SPUISD::VEC2HALF] = "SPUISD::VEC2HALF";
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}
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std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
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@ -738,12 +743,14 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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DebugLoc dl = Op.getDebugLoc();
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unsigned alignment = SN->getAlignment();
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const bool isVec = VT.isVector();
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EVT eltTy = isVec ? VT.getVectorElementType(): VT;
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switch (SN->getAddressingMode()) {
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case ISD::UNINDEXED: {
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// The vector type we really want to load from the 16-byte chunk.
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EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
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VT, (128 / VT.getSizeInBits()));
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eltTy, (128 / eltTy.getSizeInBits()));
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SDValue alignLoadVec;
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SDValue basePtr = SN->getBasePtr();
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@ -752,7 +759,6 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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if (alignment == 16) {
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ConstantSDNode *CN;
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// Special cases for a known aligned load to simplify the base pointer
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// and insertion byte:
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if (basePtr.getOpcode() == ISD::ADD
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@ -776,6 +782,9 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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} else {
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// Unaligned load: must be more pessimistic about addressing modes:
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@ -812,8 +821,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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DAG.getConstant(0, PtrVT));
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}
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// Re-emit as a v16i8 vector load
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alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
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// Load the memory to which to store.
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alignLoadVec = DAG.getLoad(vecVT, dl, the_chain, basePtr,
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SN->getSrcValue(), SN->getSrcValueOffset(),
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SN->isVolatile(), SN->isNonTemporal(), 16);
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@ -844,11 +853,19 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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}
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#endif
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SDValue insertEltOp =
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DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
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SDValue vectorizeOp =
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DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
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SDValue insertEltOp;
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SDValue vectorizeOp;
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if (isVec)
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{
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// FIXME: this works only if the vector is 64bit!
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insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v2i64, insertEltOffs);
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vectorizeOp = DAG.getNode(SPUISD::HALF2VEC, dl, vecVT, theValue);
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}
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else
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{
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insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
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vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
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}
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result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
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vectorizeOp, alignLoadVec,
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DAG.getNode(ISD::BIT_CONVERT, dl,
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@ -54,6 +54,8 @@ namespace llvm {
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ADD64_MARKER, ///< i64 addition marker
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SUB64_MARKER, ///< i64 subtraction marker
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MUL64_MARKER, ///< i64 multiply marker
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HALF2VEC, ///< Promote 64 bit vector to 128 bits
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VEC2HALF, ///< Extract first 64 bits from 128 bit vector
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LAST_SPUISD ///< Last user-defined instruction
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};
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}
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@ -1468,6 +1468,9 @@ class ORCvtGPRCVec:
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class ORCvtVecGPRC:
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ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>;
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class ORCvtVecVec:
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ORCvtForm<(outs VECREG:$rT), (ins VECREG:$rA)>;
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multiclass BitwiseOr
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{
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def v16i8: ORVecInst<v16i8>;
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@ -1514,6 +1517,13 @@ multiclass BitwiseOr
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def f32_v4f32: ORExtractElt<R32FP>;
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def f64_v2f64: ORExtractElt<R64FP>;
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// half <-> full vector mappings
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def v2i32_v4i32: ORCvtVecVec;
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def v4i32_v2i32: ORCvtVecVec;
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def v2f32_v4f32: ORCvtVecVec;
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def v4f32_v2f32: ORCvtVecVec;
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// Conversion from vector to GPRC
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def i128_vec: ORCvtVecGPRC;
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@ -1623,6 +1633,18 @@ def : Pat<(SPUvec2prefslot (v2f32 VECREG:$rA)),
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def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
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(ORf64_v2f64 VECREG:$rA)>;
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// Conversions between 64 bit and 128 bit vectors.
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def : Pat<(v4i32 (SPUhalf2vec (v2i32 VECREG:$rA))),
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(ORv4i32_v2i32 (v2i32 VECREG:$rA))>;
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def : Pat<(v4f32 (SPUhalf2vec (v2f32 VECREG:$rA))),
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(ORv4f32_v2f32 (v2f32 VECREG:$rA))>;
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def : Pat<(v2i32 (SPUvec2half (v4i32 VECREG:$rA))),
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(ORv2i32_v4i32 VECREG:$rA)>;
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def : Pat<(v2f32 (SPUvec2half (v4f32 VECREG:$rA))),
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(ORv2f32_v4f32 VECREG:$rA)>;
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// Load Register: This is an assembler alias for a bitwise OR of a register
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// against itself. It's here because it brings some clarity to assembly
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// language output.
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@ -117,6 +117,12 @@ def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>;
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def SPU_vec_demote : SDTypeProfile<1, 1, []>;
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def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
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def SPU_half_2_vec : SDTypeProfile<1, 1, []>;
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def SPUhalf2vec: SDNode<"SPUISD::HALF2VEC", SPU_half_2_vec, []>;
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def SPU_vec_2_half : SDTypeProfile<1, 1, []>;
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def SPUvec2half: SDNode<"SPUISD::VEC2HALF", SPU_vec_2_half, []>;
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// Address high and low components, used for [r+r] type addressing
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def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
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def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
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@ -587,6 +587,7 @@ SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
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case SPU::LQDr32: return SPU::LQXr32;
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case SPU::LQDr128: return SPU::LQXr128;
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case SPU::LQDv16i8: return SPU::LQXv16i8;
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case SPU::LQDv4i32: return SPU::LQXv4i32;
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case SPU::LQDv4f32: return SPU::LQXv4f32;
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case SPU::STQDr32: return SPU::STQXr32;
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case SPU::STQDr128: return SPU::STQXr128;
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=cellspu -o %t1.s
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; RUN: grep lqx %t1.s | count 4
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; RUN: grep il %t1.s | grep -v file | count 7
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; RUN: grep stqx %t1.s | count 2
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; RUN: grep lqx %t1.s | count 3
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; RUN: grep il %t1.s | grep -v file | count 5
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; RUN: grep stqx %t1.s | count 1
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define i32 @bigstack() nounwind {
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entry:
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@ -61,3 +61,15 @@ define %vec @test_insert(){
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ret %vec %rv
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}
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define void @test_unaligned_store() {
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;CHECK: cdd $3, 8($3)
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;CHECK: lqd
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;CHECK: shufb
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;CHECK: stqd
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%data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1]
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%ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1]
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%vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1]
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store <2 x float> undef, <2 x float>* %vptr
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ret void
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}
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