From 9967c15183e023b7cf59b094d69530ffeca1aa0f Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 26 Jan 2008 01:05:42 +0000 Subject: [PATCH] don't bother making x&-1 only to simplify it in dag combine. This commonly occurs expanding i64 ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46383 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index efbaa5a7f6d..ad6cd1ba3db 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1877,6 +1877,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, // worth handling here. if (N2C && N2C->getValue() == 0) return N2; + if (N2C && N2C->isAllOnesValue()) // X & -1 -> X + return N1; break; case ISD::OR: case ISD::XOR: