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MIR Serialization: Serialize physical register machine operands.

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This commit introduces functionality that's used to serialize machine operands.
Only the physical register operands are serialized by this commit.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10525


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz
2015-06-23 16:35:26 +00:00
parent a99d1c85a8
commit 9982d6f7ee
8 changed files with 296 additions and 4 deletions
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50
lib/CodeGen/MIRPrinter.cpp
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@@ -50,6 +50,7 @@ public:
MIPrinter(raw_ostream &OS) : OS(OS) {}
void print(const MachineInstr &MI);
void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
};
} // end anonymous namespace
@@ -110,11 +111,58 @@ void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
void MIPrinter::print(const MachineInstr &MI) {
const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
const auto *TRI = SubTarget.getRegisterInfo();
assert(TRI && "Expected target register info");
const auto *TII = SubTarget.getInstrInfo();
assert(TII && "Expected target instruction info");
unsigned I = 0, E = MI.getNumOperands();
for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
!MI.getOperand(I).isImplicit();
++I) {
if (I)
OS << ", ";
print(MI.getOperand(I), TRI);
}
if (I)
OS << " = ";
OS << TII->getName(MI.getOpcode());
// TODO: Print the instruction flags, machine operands, machine mem operands.
// TODO: Print the instruction flags, machine mem operands.
if (I < E)
OS << ' ';
bool NeedComma = false;
for (; I < E; ++I) {
if (NeedComma)
OS << ", ";
print(MI.getOperand(I), TRI);
NeedComma = true;
}
}
static void printReg(unsigned Reg, raw_ostream &OS,
const TargetRegisterInfo *TRI) {
// TODO: Print Stack Slots.
// TODO: Print no register.
// TODO: Print virtual registers.
if (Reg < TRI->getNumRegs())
OS << '%' << StringRef(TRI->getName(Reg)).lower();
else
llvm_unreachable("Can't print this kind of register yet");
}
void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
switch (Op.getType()) {
case MachineOperand::MO_Register:
// TODO: Print register flags.
printReg(Op.getReg(), OS, TRI);
// TODO: Print sub register.
break;
default:
// TODO: Print the other machine operands.
llvm_unreachable("Can't print this machine operand at the moment");
}
}
void llvm::printMIR(raw_ostream &OS, const Module &M) {