From 99906830e82cf70dbcbed22237c7bd24f9d9ffdb Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor@mac.com>
Date: Thu, 25 Aug 2011 18:30:18 +0000
Subject: [PATCH] Port over additional encoding tests to decoding tests, and
 fix an operand ordering bug this exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../ARM/Disassembler/ARMDisassembler.cpp      |  2 +-
 test/MC/Disassembler/ARM/thumb1.txt           | 31 +++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 83a8f800608..0d945fdf591 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
     Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
 
     CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
-    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
     CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
   } else if (Inst.getOpcode() == ARM::tADDspr) {
     unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
 
diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt
index d07cd84abce..3e0722d32ef 100644
--- a/test/MC/Disassembler/ARM/thumb1.txt
+++ b/test/MC/Disassembler/ARM/thumb1.txt
@@ -28,6 +28,29 @@
 0xd1 0x18
 0x42 0x44
 
+#------------------------------------------------------------------------------
+# ADD (SP plus immediate)
+#------------------------------------------------------------------------------
+# CHECK: add sp, #508
+# CHECK: add sp, #4
+# CHECK: add r2, sp, #8
+# CHECK: add r2, sp, #1020
+
+0x7f 0xb0
+0x01 0xb0
+0x02 0xaa
+0xff 0xaa
+
+
+#------------------------------------------------------------------------------
+# ADD (SP plus register)
+#------------------------------------------------------------------------------
+# CHECK: add sp, r3
+# CHECK: add r2, sp, r2
+
+0x9d 0x44
+0x6a 0x44
+
 #------------------------------------------------------------------------------
 # ASR (immediate)
 #------------------------------------------------------------------------------
@@ -442,6 +465,14 @@
 
 0xd1 0x1a
 
+#------------------------------------------------------------------------------
+# SUB (SP minus immediate)
+#------------------------------------------------------------------------------
+# CHECK: sub sp, #12
+# CHECK: sub sp, #508
+
+0x83 0xb0
+0xff 0xb0
 
 #------------------------------------------------------------------------------
 # SVC