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Add new immed16.ll test case, fix CellSPU errata to make test case work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45196 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -597,7 +597,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
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DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
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DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
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return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
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CurDAG->getTargetConstant(0, MVT::i32));
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} else if (Opc == SPUISD::LDRESULT) {
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@ -670,6 +670,11 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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SDOperand ptrOp;
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int offset;
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if (basep.getOpcode() == ISD::FrameIndex) {
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// FrameIndex nodes are always properly aligned. Really.
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return SDOperand();
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}
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if (basep.getOpcode() == ISD::ADD) {
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const ConstantSDNode *CN = cast<ConstantSDNode>(basep.Val->getOperand(1));
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assert(CN != NULL
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@ -694,13 +699,10 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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stVecVT = MVT::v16i8;
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vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
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// Realign the pointer as a D-Form address (ptrOp is the pointer,
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// to force a register load with the address; basep is the actual
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// dform addr offs($reg).
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ptrOp = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
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DAG.getConstant(0, PtrVT));
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basep = DAG.getNode(SPUISD::DFormAddr, PtrVT,
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ptrOp, DAG.getConstant((offset & ~0xf), PtrVT));
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// Realign the pointer as a D-Form address (ptrOp is the pointer, basep is
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// the actual dform addr offs($reg).
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basep = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
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DAG.getConstant((offset & ~0xf), PtrVT));
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// Create the 16-byte aligned vector load
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SDOperand alignLoad =
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@ -62,7 +62,6 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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case SPU::AHIvec:
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case SPU::AHIr16:
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case SPU::AIvec:
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case SPU::AIr32:
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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@ -74,6 +73,19 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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return true;
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}
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break;
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case SPU::AIr32:
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assert(MI.getNumOperands() == 3 &&
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"wrong number of operands to AIr32");
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if (MI.getOperand(0).isRegister() &&
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(MI.getOperand(1).isRegister() ||
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MI.getOperand(1).isFrameIndex()) &&
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(MI.getOperand(2).isImmediate() &&
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MI.getOperand(2).getImmedValue() == 0)) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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#if 0
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case SPU::ORIf64:
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case SPU::ORIf32:
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@ -3476,10 +3476,8 @@ def : Pat<(SPUdform tjumptable:$in, imm:$imm), (ILAlsa tjumptable:$in)>;
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// Force load of global address to a register. These forms show up in
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// SPUISD::DFormAddr pseudo instructions:
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/*
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def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
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def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
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def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
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*/
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// Instrinsics:
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include "CellSDKIntrinsics.td"
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@ -585,8 +585,6 @@ void
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SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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assert(SPAdj == 0 && "Unexpected SP adjacency == 0");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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38
test/CodeGen/CellSPU/immed16.ll
Normal file
38
test/CodeGen/CellSPU/immed16.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep "ilh" %t1.s | count 5
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define i16 @test_1() {
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%x = alloca i16, align 16
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store i16 419, i16* %x ;; ILH via pattern
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ret i16 0
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}
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define i16 @test_2() {
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%x = alloca i16, align 16
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store i16 1023, i16* %x ;; ILH via pattern
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ret i16 0
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}
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define i16 @test_3() {
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%x = alloca i16, align 16
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store i16 -1023, i16* %x ;; ILH via pattern
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ret i16 0
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}
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define i16 @test_4() {
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%x = alloca i16, align 16
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store i16 32767, i16* %x ;; ILH via pattern
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ret i16 0
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}
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define i16 @test_5() {
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%x = alloca i16, align 16
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store i16 -32768, i16* %x ;; ILH via pattern
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ret i16 0
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}
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define i16 @test_6() {
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ret i16 0
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}
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