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Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2011-04-15 19:52:08 +00:00
parent b6a638898a
commit 99a2e98edd
9 changed files with 196 additions and 9 deletions
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27
test/CodeGen/Mips/buildpairextractelementf64.ll Normal file
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@@ -0,0 +1,27 @@
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
@a = external global i32
define double @f(i32 %a1, double %d) nounwind {
entry:
; CHECK-EL: mtc1 $6, $f12
; CHECK-EL: mtc1 $7, $f13
; CHECK-EB: mtc1 $7, $f12
; CHECK-EB: mtc1 $6, $f13
store i32 %a1, i32* @a, align 4
%add = fadd double %d, 2.000000e+00
ret double %add
}
define void @f3(double %d, i32 %a1) nounwind {
entry:
; CHECK-EL: mfc1 ${{[0-9]+}}, $f12
; CHECK-EL: mfc1 $7, $f13
; CHECK-EB: mfc1 ${{[0-9]+}}, $f13
; CHECK-EB: mfc1 $7, $f12
tail call void @f2(i32 %a1, double %d) nounwind
ret void
}
declare void @f2(i32, double)