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TargetSchedModel interface. To be implemented...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8
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include/llvm/CodeGen/TargetSchedule.h
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63
include/llvm/CodeGen/TargetSchedule.h
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//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a wrapper around MCSchedModel that allows the interface to
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// benefit from information currently only available in TargetInstrInfo.
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// Ideally, the scheduling interface would be fully defined in the MC layter.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
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#define LLVM_TARGET_TARGETSCHEDMODEL_H
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/MCInstrItineraries.h"
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namespace llvm {
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class TargetRegisterInfo;
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class TargetSubtargetInfo;
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class TargetInstrInfo;
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class MachineInstr;
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/// Provide an instruction scheduling machine model to CodeGen passes.
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class TargetSchedModel {
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// For efficiency, hold a copy of the statically defined MCSchedModel for this
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// processor.
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MCSchedModel SchedModel;
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InstrItineraryData InstrItins;
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const TargetSubtargetInfo *STI;
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const TargetInstrInfo *TII;
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public:
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TargetSchedModel(): STI(0), TII(0) {}
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void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
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const TargetInstrInfo *tii);
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const TargetInstrInfo *getInstrInfo() const { return TII; }
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/// Return true if this machine model includes an instruction-level scheduling
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/// model. This is more detailed than the course grain IssueWidth and default
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/// latency properties, but separate from the per-cycle itinerary data.
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bool hasInstrSchedModel() const {
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return SchedModel.hasInstrSchedModel();
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}
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/// Return true if this machine model includes cycle-to-cycle itinerary
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/// data. This models scheduling at each stage in the processor pipeline.
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bool hasInstrItineraries() const {
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return SchedModel.hasInstrItineraries();
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}
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unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
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};
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} // namespace llvm
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#endif
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@ -199,6 +199,8 @@ public:
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MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
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SchedClassTable(0), InstrItineraries(ii) {}
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unsigned getProcessorID() const { return ProcID; }
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/// Does this machine model include instruction-level scheduling.
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bool hasInstrSchedModel() const {
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return SchedClassTable;
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@ -118,6 +118,9 @@ public:
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/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
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///
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InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
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/// Initialize an InstrItineraryData instance.
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void initInstrItins(InstrItineraryData &InstrItins) const;
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};
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} // End llvm namespace
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@ -102,6 +102,7 @@ add_llvm_library(LLVMCodeGen
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TargetInstrInfoImpl.cpp
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TargetLoweringObjectFileImpl.cpp
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TargetOptionsImpl.cpp
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TargetSchedule.cpp
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TwoAddressInstructionPass.cpp
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UnreachableBlockElim.cpp
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VirtRegMap.cpp
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32
lib/CodeGen/TargetSchedule.cpp
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lib/CodeGen/TargetSchedule.cpp
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//===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a wrapper around MCSchedModel that allows the interface
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// to benefit from information currently only available in TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
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cl::desc("Use TargetSchedModel for latency lookup"));
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void TargetSchedModel::init(const MCSchedModel &sm,
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const TargetSubtargetInfo *sti,
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const TargetInstrInfo *tii) {
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SchedModel = sm;
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STI = sti;
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TII = tii;
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STI->initInstrItins(InstrItins);
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}
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@ -101,3 +101,9 @@ MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
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return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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}
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/// Initialize an InstrItineraryData instance.
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void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
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InstrItins =
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InstrItineraryData(0, Stages, OperandCycles, ForwardingPaths);
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}
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