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ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Xerxes Ranby 2010-07-22 17:28:34 +00:00
parent 481c4c0734
commit 99ccffe87e
2 changed files with 14 additions and 1 deletions
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13
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -654,6 +654,19 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
switch (Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
case ARM::BX:
case ARM::BMOVPCRX:
case ARM::BXr9:
case ARM::BMOVPCRXr9: {
// First emit mov lr, pc
unsigned Binary = 0x01a0e00f;
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
emitWordLE(Binary);
// and then emit the branch.
emitMiscBranchInstruction(MI);
break;
}
case TargetOpcode::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.

2
lib/Target/ARM/ARMInstrFormats.td
View File

@ -313,7 +313,7 @@ class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
}
class ABXIx2<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
asm, "", pattern>;
// BR_JT instructions