mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-08 06:32:24 +00:00
[ARM] Register (existing) ARMLoadStoreOpt pass with LLVM pass manager.
Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243052 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
5fb71b264d
commit
99d1c88279
@ -60,12 +60,20 @@ STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
|
||||
STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
|
||||
STATISTIC(NumSTRD2STR, "Number of strd instructions turned back into str's");
|
||||
|
||||
namespace llvm {
|
||||
void initializeARMLoadStoreOptPass(PassRegistry &);
|
||||
}
|
||||
|
||||
#define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
|
||||
|
||||
namespace {
|
||||
/// Post- register allocation pass the combine load / store instructions to
|
||||
/// form ldm / stm instructions.
|
||||
struct ARMLoadStoreOpt : public MachineFunctionPass {
|
||||
static char ID;
|
||||
ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
|
||||
ARMLoadStoreOpt() : MachineFunctionPass(ID) {
|
||||
initializeARMLoadStoreOptPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
const MachineFunction *MF;
|
||||
const TargetInstrInfo *TII;
|
||||
@ -84,7 +92,7 @@ namespace {
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
const char *getPassName() const override {
|
||||
return "ARM load / store optimization pass";
|
||||
return ARM_LOAD_STORE_OPT_NAME;
|
||||
}
|
||||
|
||||
private:
|
||||
@ -148,6 +156,8 @@ namespace {
|
||||
char ARMLoadStoreOpt::ID = 0;
|
||||
}
|
||||
|
||||
INITIALIZE_PASS(ARMLoadStoreOpt, "arm-load-store-opt", ARM_LOAD_STORE_OPT_NAME, false, false)
|
||||
|
||||
static bool definesCPSR(const MachineInstr *MI) {
|
||||
for (const auto &MO : MI->operands()) {
|
||||
if (!MO.isReg())
|
||||
|
Loading…
x
Reference in New Issue
Block a user